Integrated circuit course

PLANNING TOOLS There needs to be a planning phase for all layout design tasks, but in general a floorplan starts from the chip level down to the block level. The idea behind this methodology is to build everything bottom-up while using the top-level floorplan to define the block interfaces and to coordinate updates to these interfaces as portions of the design are completed or verified. Chip Floorplanning Tools Floorplanning is the process of identifying structures that should be placed together and allocating space for them so as to meet the conflicting goals of avail- able space (cost of the chip), required performance, and the desire to have every block connect seamlessly to everything else. In most chips, the smallest design is also the highest performance design. Therefore, area and speed are characteristics that go hand-in-hand. A block or chip that is small in area has shorter interconnect lines, less routing, faster end-to-end signal paths, and even faster and more consisten...

SUPPORT TOOLS In terms of layout entry, we have covered the basic types of tools involved. The design process is not only layout entry. The layout needs to be verified against various quality standards, and manufacturing design rules and layout can be migrated from other sources to save time and effort. Tools that perform all of these operations will be covered in this section, as well as a discussion of standard data- base formats used for layout today. Layout Verification Tools Figure 10.7 documents the layout design procedure as discussed in Chapter 3. The highlighted steps correspond to a verification tool that is discussed in this section. It is important to remember that layout verification must be done on the entire chip and on the file that is to be sent to manufacturing. DRC/LVS/ERC. The verification of a full chip database file has been an issue for the verification tools over the course of time as designs have grown from 1,000 to 10,000,000 transistors. As the designs have g...

PLANNING FOR UNKNOWN CHANGES During various phases of design, layout designers are challenged with design rule changes, circuit changes, bugs in the software tools, etc. The best medication is prevention, but we don’t always know what to expect. In a DRAM chip, if any of the major memory layers gets a minor design rule change, it may not be efficient to use the planned architecture, so the entire core layout and design should change. Such process changes have much less impact on the layout of ASIC designs, because their processes are much simpler and because most of the layout is done using place-and-route tools. Planning for unknown changes might seem strange at first, but we can always estimate the amount of change of a particular design based on the novelty of the design and the experience of the circuit designers. In general, when planning at the chip level, most numbers are “wet finger” values. Even using the most advanced tools for floorplanning, there is no way to envision the fi...

LAYOUT GENERATION TOOLS Layout generation tools are the main bulk of the layout design tools on the market today. Different tools are used depending on the level of abstraction, and this ranges from cell- or transistor-based layout to chip assembly. Each of these will be covered in this section. Cell-Level Layout Generation Tools Cell-level layout generation tools manipulate polygons to form transistors and connections between them. Polygon Pusher. The most popular tool for cell-level layout generation is still the “polygon pusher” or basic “layout editor.” Theoretically, a polygon pusher can be used to design a complete chip of any kind from transistor level and up. However, it is not practical for block or chip assembly. Polygon pushers are used to generate low-level cells, ranging from 10 to 100 transistors, and for drawing all the layers required in a VLSI process. These tools are very mature, and generally minimum maintenance is required. However, some companies have inv...

INTRODUCTION Every year at the biggest conference for IC CAD known as the Design Automation Conference, VLSI designers from around the world are bombarded with names of new products and methodologies that can improve the efficiency of design. Before the conference, magazine and e-mail advertising is frenzied, and during the conference, presentations and demonstrations are given all day long. In all of them the marketing and salespeople presenting the tools always feature new options and benefits such as extra capacity and quality, a variety of menu options, and the very “important” price/performance ratio in comparison to manual methods or tools from the competition. None of these presentations discuss the philosophy of the tool, what the designer of the tool had in mind, what new concepts the tool is addressing, or what kind of flow the tool is supporting. We learn about buttons, ease of use features, values to enter into forms, but not the real reason why we should use the tool. I...