Multidimensional Logarithmic Number System:Fabricated Designs

By -
Fabricated Designs

As an example of the applicability of the MDLNS representation to DSP applications, a variety of digital filters using the architecture proposed in Section 84.3.2 have been created. These designs have used both one- and two-digit 2DLNS representations with different bases.

Multidimensional Logarithmic Number System-0195

Two-Digit Data, One-Digit Coefficient Parallel Design

A two-digit 2DLNS architecture for a 15-tap filter has been fabricated (TSMC 0.35 µm three-metal CMOS process) and successfully tested [12,20]. The input data (10-bit 2’s complement converted via an LUT) uses the full two-digit representation, but the filter coefficients are designed using a one-digit MDLNS (a hybrid representation). This requires two inner product computational units per coefficient. The chip size is very large at 9 mm X 16 mm, owing to the 1024-word LUT in each of the inner product computational units which are implemented with logic gates and only three layers of metal. Although impractical in terms of the large area of silicon used, it was the first MDLNS circuit fabrication and also allowed design comparisons based solely on representation choices and not on design skill. The layout is shown in Figure 84.15 and the two parallel arrays are clearly visible.

Multidimensional Logarithmic Number System-0196

Two-Digit Data and Coefficient Serial Design

An eight-band 75-tap filterbank [30] designed for use in a low-power digital hearing instrument (fabricated in a TSMC 0.18 mm six-metal CMOS process) uses a two-digit data and coefficient 2DLNS system. The input binary data (16-bit 2’s complement) is converted to 2DLNS using a two-digit 2DLNS high/low serial converter. The system uses a four-channel architecture with each channel utilizing a 2DLNS to binary LUT containing 32 words. The filter coefficient’s optimal second base range is limited to only 2 bits. Since the filterbank is intended for processing speech and low-power operation, a serial implementation was selected to minimize both power and area. The design consumes 708 mW and the core size is 1 mm X 1 mm, half of which is occupied by the converter as the RALUT is built using standard cells (see Figure 84.16).

A second-generation unfabricated design [31] promises half the power (316 mW), almost half the logic cells, and one-third of the area (555 µm X 555 µm). These improvements are the result of utilizing an optimal base on the input data versus the filter coefficients, single-phase operation, single-port RAM, and a single sign-bit architecture.

Complexity Reduction

Although the two designs are fabricated in different technologies, one can see that the thirty 1024-word LUTs dominate the area of the 15-tap filter. Assuming a technology scaling factor of 2, over 200 of the second-generation 75-tap filter designs can be placed in the same area as that of the 15-tap filter. This clearly shows the benefit of using a full multiple-digit MDLNS.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more