Architecture:Instruction Set Architecture

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Instruction Set Architecture

There are several elements that characterize an instruction set architecture, word size, instruction encoding, and architecture style.

Word Size

Programs often differ in the size of data they prefer to manipulate. Word processing programs operate on 8- or 16-bit data that correspond to characters in text documents. Many applications require 32-bit integer data to avoid frequent overflow in arithmetic calculation. Scientific computation often require 64-bit floating-point data to achieve desired accuracy. Operating systems and data bases may require 64-bit integer data to represent a very large name space with integers. As a result, the processors are usually designed to access data of a variety of sizes from memory systems. This is a well-known source of complexity in microprocessor design.

The endian convention specifies the numbering of bytes within a memory word. In the little endian convention, the least significant byte in a word is numbered byte 0. The number increases as the positions increase in significance. The DEC VAX and X86 architectures follow the little endian convention. In the big endian convention, the most significant byte in a word is numbered 0. The number decreases as the positions decrease in significance. The IBM 360/370, HP PA-RISC, SUN SPARC, and Motorola 680X0 architectures follow the big endian convention. The endian convention determines how the word is stored in the address space or in a binary file. The difference usually manifest itself when users try to transfer binary files between machines using different endian conventions.

Instruction Encoding

Instruction encoding plays an important role in the code density and performance of microprocessors. Traditionally, the cost of memory capacity was the determining factor in designing either a fixed-length or variable-length instruction set. Fixed-length instruction encoding assigns the same encoding size to all instructions. Fixed-length encoding is generally a product of the increasing advancements in memory capacity.

Variable length instruction set is the term used to describe the style of instruction encoding that uses different instructions lengths according to addressing modes of operands. Common addressing modes included either register or methods of indexing memory. Figure 66.10 illustrates two potential designs found in modern use of decoding variable length instructions. The first alternative in Figure 66.10(a) involves an additional instruction decode stage in the original pipeline design. In this model, the first stage is used to determine instruction lengths and steer the instructions to the second stage where the actual instruction decoding is performed. The second alternative in Figure 66.10(b) involves predecoding and marking instruction lengths in the instruction cache. The primary advantage of this scheme is the simplification of the number of decode stages in the pipeline design. However, the method requires a larger instruction cache structure for holding the resolved instruction information. Both design methodologies have been effectively used in decoding X86 variable instructions [5].

Architecture Style

Several instruction set architecture styles have existed over the past three decades of computing. First, complex instruction set computers (CISC) characterized designs with variable instruction formats, numerous memory addressing modes, and large numbers of instruction types. The original CISC philosophy was to create instructions sets that resembled high-level programming languages in an effort to simplify compiler technology. In addition, the design constraint of small memory capacity also led to the development of CISC. Two examples of the CISC model are the Digital Equipment Corporation VAX and Intel X86 architecture families.

Reduced instruction set computers (RISC) gained favor with the philosophy of uniform instruction lengths, load-store instruction sets, limited addressing modes, and reduced number of operation types. RISC concepts allow the micro-architecture design of machines to be more easily pipelined, reducing

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the processor clock cycle frequency and the overall speed of a machine. The RISC concept resulted from improvements in compiler technology and memory size. The HP PA-RISC, Sun SPARC, IBM Power PC, MIPS, and DEC Alpha machines are examples of RISC architectures.

Architecture models that specify multiple operations to issue in a clock cycle are VLIW (very long instruction word). VLIWs issue a fixed number of operations conveyed as a single long instruction and place the responsibility of creating the parallel instruction packet on the compiler. Early VLIW processor suffered from code expansion due to unfilled operation slots in the long instructions. Examples of VLIW technology are the Multiflow Trace, Cydrome Cydra machines, and TI-C6X. Explicitly parallel instruction computing (EPIC) is similar in concept to VLIW in that both use the compiler to explicitly group instructions for parallel execution. In fact, many of the ideas for EPIC architectures come from previous RISC and VLIW machines. In general, the EPIC concept solves the excessive code expansion and scalability problems associated with VLIW models by providing encoding mechanisms to reduce the need to represent unfilled operation slots in long instructions. Also, the trend of compiler-controlled architecture mechanisms such as predicated execution and speculative execution to be described later in this section are generally considered part of the EPIC style architecture domain. The Intel IA-64, Philips Trimedia, and Lucent/Motorola StarCore are examples of EPIC machines.

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