LAYOUT DESIGN:FINAL STEPS

FINAL STEPS

Despite tremendous advances over the past 10 years in tools for IC design, and despite the best intentions of the top designers, there is always room for improvement and opportunity for something to be overlooked. The complexity and variety of process design rules over time also creates new challenges to old problems. For these reasons, a final sanity and cross-check in the form of an audit is time well spent (Figure 3.34).

Compared to many, many years ago, audit checklists today may be smaller, but the burden has simply shifted to the personnel responsible for the setup and maintenance of the layout CAD tools and layout flow. CAD verification tools

check many issues, but it still takes a knowledgeable person to ensure that the tools are doing their job.

The secret of proper audit results is to have an auditor who understands the concepts behind the issues and the extent of any problem, and who can also propose solutions. It is a good idea to have a third-party auditor: a person who has not been directly involved in the project or design being audited. This eliminates any predisposed bias or assumptions.

The procedure is straightforward. The auditor should review the requirements and documentation for the design and, using checklists specific to the type and complexity of the design involved, verify the final design against these requirements. The checklist generated in the floorplanning step is a prime example of documentation for the design.

Issues that are raised are documented. At this point it is a good idea to involve the circuit designer in the audit process as well as the person responsible for integrating the design into the next higher level. This way a solution to any problem identified can be dealt with efficiently and with all the relevant information at hand.

All issues are signed off by the auditor who identified the problems, once the solutions have been implemented.

The very last step in the process is to generate an extracted layout.

Extraction is a hand-off step back to the circuit designer. A version of the final layout design compatible for simulation is given back to the circuit designer for final resimulation. Tweaks to the design may occur after simulation.

Extraction is the process of automatically generating from the layout a netlist compatible for simulation that includes information that corresponds with all the device connectivity, device sizes, and routing capacitance and resistance.

The extracted netlist is a good communication mechanism between the layout and circuit designer. It also indicates that the layout design is complete pending the final simulation result.

Verifications

In terms of verifications of the final files, here are some considerations.

Because the mask shop requires GDSII file type, the final verification will be done on the same file that goes to manufacturing. If the layers shipped to the mask shop are different from the ones used for design, the final verification has to be done on the GDSII required by the mask. The database has to be translated from the design layers that were used and verified online into the mask shop layers and verified as the final “golden” verification. However, there are a few structures that we add for the processing needs that won’t pass DRC or LVS verifications without errors. These structure-generated errors must be checked very carefully, and not ignored, because they can touch real sensible logic circuitry, and then we have a problem.

Most important factor is that the final verification be done using “frozen” GDSII generated from a “frozen” database, which means that nobody can touch the original online data. This way you can ensure unique data.

Audits

At this level audits have to be performed by an experienced person who has already passed through one or more tape-outs. As a baseline check, the layout designer can use the checklist provided earlier, adding any company- and process- related questions. The other important issue is to audit the newly placed keys that may not conform to the DRC command file. (Refer to the checklist.)

A very important task, that is sometimes forgotten, is to re-audit the design if the command files for DRC and LVS include verifications for layers that are not designed in layout but generated using CAD software before mask making. One example is the N+ layer that surrounds the N transistors placed on the P+ substrate. In general, it is not drawn by layout designers and is generated only before mask manufacturing. In our experience, we have found that layers like this can generate problems if they are not checked before mask preparation.

Tape-out Procedures

When people talk about tape out procedures they are referring to the steps detailed above plus specific documentation sign offs and release procedures. For each chip released to the mask shop, there are internal company procedures that have to be followed. For example, the division management, together with the project leaders and the circuit and layout designers, should review all audit reports, additional company standard sign off procedures, and sign and release the tape and the accompanying documents and data.

It is a good practice to take care that all the macros, documents, verification results, audit reports, and command files related to the chip that has been taped out are filed for easy access in future releases. If there are any problems with the released project, it will be easy to access all the related setups and documents.