LAYOUT DESIGN:VERIFICATION

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VERIFICATION

Now that the implementation of the layout is complete, we move to the verification step (Figure 3.33). This is not a small task, and it is a very important one. There are many failure mechanisms in IC design, and fixing errors is very expensive. Unlike fixing a car, where access to components for replacement and modification is rela- tively quick and easy, fixing design errors can take months. We should take the approach that we only have one chance to get our design right, because a revision to a design is a very lengthy and costly process (somewhat like trying to fix a satellite after it is in orbit—possible, these days, but extremely costly).

In spite of all of the planning and checklists, a robust verification plan is required for best results. Each step in the plan checks different aspects of the design.

Design Rules Check (DRC)

The design rule verification step checks that all polygons and layers from the layout database meet all of the manufacturing process rules. As described in Section 3.4, these design rules define the limits of a manufacturable design. Width and space rules fall into this category.

Meeting the manufacturing requirements is the absolute minimum rule set that must be checked and corrected. Because this is the first level of verification once the layout is implemented, typically many methodology, connectivity, and guideline rules are checked as well. We refer to these as a set of supplementary rules. An example would be an illegal use of layers (ESD layer in the logic area) or illegal devices or connections.

Tip: A truly complete DRC verification approach would be to verify not only the design that you, as a designer, have implemented, but also your design placed within the context in which it is going to be used.

If the specific components that will interface or be adjacent to your design are available, perform a DRC check with this interface cell included. If your cell is a general-purpose design, then a more intricate and exhaustive check should be performed, perhaps including all possible interface cells as well as different

Layout Design-0047

orientations and combinations that may occur. These approaches really eliminate the possibility of errors as your design is integrated into the overall chip.

Layout versus Schematic (LVS)

LVS verification is checking that the design is connected correctly. The schematic is the reference circuit and the layout is checked against it. In principle, the fol- lowing is verified:

• Electrical connectivity of all signals, including input, output, and power signals to their corresponding devices

• Device sizes: transistor width and length, resistor sizes, capacitor sizes

• Identification of extra components and signals that have not been included in the schematic; floating nodes would be an example of this

The last item overlaps into the items checked in the electrical rules check, which is described next.

Electrical Rules Check (ERC)

As noted in Figure 3.33 the ERC is sometimes an optional or seldom used as an independent verification step. Many of the issues are caught by the LVS check, and thus the ERC has become redundant.

Electrical rules checked in this step are usually limited to errors in connectivity or device connection. Examples include the following:

• Unconnected, partly connected, or extra devices

• Disabled transistors

• Floating nodes

• Short circuits

• Special checks not checked elsewhere (i.e., antenna rules)

As a subset of the LVS check, an ERC generally executes more quickly and therefore is useful to accelerate debugging problems such as a VDD-to-VSS short circuit.

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