System Verilog:System Verilog Origin and Basic Concepts

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System Verilog Origin

Verilog HDL and several CAD tools, e.g., simulation tools, synthesis tools, and verification tools, were designed in 1984 by Gateway Design Automation. In 1990, the Open Verilog International (OVI) was formed and efforts for Verilog HDL popularization were started. These efforts led to the standard Verilog HDL as IEEE 1364 Verilog HDL (Verilog-95). In the late 1990s, the need for using higher level constructs for system level design increased. As a result some new features were added to Verilog-95 and the language was specified as the IEEE 1364 Verilog-2001. Since then several EDA companies and committees worked on Verilog-2001 and finally in May 2002 it was finalized as the System Verilog 3.0 standard [1,2,3].

Basic Concepts
Data Types

There are several built-in data types in Verilog-95, such as net, reg, and integer. In System Verilog, these data types are extended to new data types that are used to ease hardware description at RTL and system level. System Verilog also allows users to define their own data types.

Verilog-95 Data Types

There are two basic data types in Verilog-95 for hardware description. These types include net and reg. Both net and reg data types use a 4-logic value system including 0, 1, Z, and X. The net data type is used to model an interconnection between two components (as an actual wire). The reg data type is used to model the behavior of the circuit (as a software variable). The usage of these types is restricted, which implies that you are only allowed to use the net type in module instantiation or in continuous assign- ments. In contrast, the reg data type should only be used in procedural assignments.

System Verilog Basic Data Types

System Verilog is backward-compatible with Verilog-95, which means that all data types in Verilog-95 can be used in System Verilog. In addition, System Verilog has several new data types, with two logic values (0 and 1) for RTL and system level description. These data types include bit, byte, shortint, int, and longint to show 1-bit, 8-bit, 16-bit, 32-bit, and 64-bit variables, respectively. Figure 90.1 shows two examples of variable declarations, including declaring a 1-bit variable named carry, and a 16-bit variable named d_in.

By default, variables declared as byte, shortint, int, and longint, are considered as signed numbers. However, they can be changed to unsigned numbers using the unsigned modifier. A variable defined as a vector of nets, regs, or bits is considered an unsigned number. The signed modifier enables us to declare a signed variable with arbitrary size. Figure 90.2 shows the declaration of an unsigned 8-bit variable sum, and a signed 12-bit variable d_out.

As described earlier, type reg is used to define a 1-bit variable. The keyword reg may mislead the user that the object corresponds to a hardware register. To avoid this misleading, a 4-logic value data type, called logic, is added in System Verilog. The logic data type has all features of type reg and can therefore be used instead of it.

Two other data types void and shortreal are used to show a function which has no return value and a 32-bit single precision floating point number, respectively.

As an example consider a signed adder with two signed 8-bit inputs a and b, a 1-bit input c_in, a signed 8-bit output sum, and a 1-bit output c_out. Figure 90.3 shows the System Verilog code for the adder that uses a continuous assign statement. In Verilog-95, ports are defined in two steps: first, module ports appear in the module definition’s list of ports and second they are declared in the module body. As shown in Figure 90.3, these two steps can be performed simultaneously in System Verilog.

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