LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS:LARGE METAL VIA IMPLEMENTATIONS.

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LARGE METAL VIA IMPLEMENTATIONS

As we have mentioned in Chapter 7, vias connecting layers together should be considered in the electromigration and resistance calculation. There are also process-related issues that should be considered.

The vias are structures that lie directly in the current path between the two layers. Thus, the layout design of interlayer connections using vias should be well understood. It is most important in large metal lines because in general it is these lines that carry large currents.

From a process point of view, vias are holes defined in the isolation layer between two layers: the top layer metal is required to fill the hole and connect to the lower layer. The manufacturing of this hole and the subsequent filling of this hole by the upper-layer metal does not result in connections that are the same size as drawn.

Figure 8.5 illustrates this effect. The design rules and electrical characteris- tics of the vias take these effects into account to ensure that a reliable via is formed. On the CD-ROM, there are more pictures of vias taken from a wafer.

Layout Design Techniques to Address Electrical Characteristics-0133

There are techniques in layout design that may increase the reliability of via arrays. Common examples of these are shown in Figure 8.6, and their usefulness depends on the process.

The ability of a line to carry current is defined by the layers width and thick- ness. This is analogous to the size of a pipe carrying water. The number of vias connecting one layer to another must be determined by a variety of conditions, starting with electromigration, resistance of the via, current flows, process specifications, and planarization.

Via array configurations that are optimized for circuit performance are shown in Figure 8.7.

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