Timing Description Languages:SDF

SDF

Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1].

Role of SDF in Design Process

SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints.

Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints.

During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations.

SDF Structure

An SDF file is in ASCII format with a structure as shown below.

An SDF file starts with the DELAYFILE keyword and is followed by a header section and one or more cell descriptions. Each cell corresponds to a part of the design and can be an ASIC library primitive, a modeling primitive for a specific analysis tool or a user-created part of the design hierarchy.

Header Section

The header of a SDF file includes documentation, physical and formatting information about the entire file. The documentation information includes version of the current SDF file, related design and vendor name, date of creation, and generating tool version and generating tool name of the current SDF file. Physical information includes the operating voltage, temperature and process factor for which the corresponding timing parameters have been evaluated, and timescale for the corre- sponding timing parameters. In addition, formatting information that represents the symbol dem- onstrating the hierarchy in the SDF file is included in the header. Among the discussed items the only required entry is the SDF version, while other entries are optional. Note that the default value for timescale is 1 ns. The hierarchy divider symbol must be either a period (.) or a slash (/) with a default value of period (.).

The first part of Figure 95.1 (lines 1 to 12) shows the header of a sample SDF file. Following the header, the cell part begins on line 14 of this figure, which will be discussed in the following sections.

Cell Section

Each cell of a design is identified by its name (CELLTYPE), hierarchical location (INSTANCE), and corresponding timing parameters. As shown in Figure 95.1, each cell starts with the CELL keyword and is followed by its type, instance, and timing specifications. These fields are discussed below:

CELLTYPE is a string that indicates the name of an ASIC library primitive or a user-created region.

INSTANCE is a string that represents the hierarchical location of the current cell in the design.

Timing specification fields of a cell (starting on line 17 of Figure 95.1) contain the actual timing data associated with that cell. Four different types of timing specifications can be used for each cell. These timing specifications are DELAY, TIMINGCHECK, TIMINGENV, and LABEL.

CELLTYPE and INSTANCE are required for identifying each cell, but timing specification fields are optional, i.e., each cell in the SDF file can include zero or more timing specifications.

Delay Values.

Each delay construct includes a list of 1, 2, 3, 6, or 12 values (see, for example, line 19 of Figure 95.1). In the case of a 12-valued list, values specify in sequence the delays corresponding to transitions in column 1 of Table 95.1. For a 2-, 3-, or 6-valued list, delay values corresponding to each transition can

be specified according to columns 2 to 4 of this table. For example in a 6-valued list, the represented values specify in sequence the delays corresponding to the first 6 transitions in column 1 of Table 95.1. In this case the related delays of other transitions are determined according to column 4 of this table. If there is only one value in the list then this value is applied to all the transition delay values. If a delay value is null, the parentheses enclosing that value is empty. This null value acts as a placeholder and allows specifications of the corresponding parameters further down the list.

Figure 95.1 shows the SDF file of a T-type flip-flop composed of a D-type flip-flop and an inverter. Line 25 of this figure shows an example of utilizing a 6-valued delay list.

A delay construct includes a list of delay values each of which is composed of a list of 1, 2, or 3 values enclosed in a pair of parentheses. An example is shown in line 45 of Figure 95.1 and will be discussed later in this section.

If a delay value contains three values, the first value specifies the delay value, while the second and the third values represent rejection limit (r-limit) and filter limit (e-limit), respectively. In addition, if a delay value is composed of two values, the first value specifies the delay value while the second value represents both limits (r- and e-limit). Finally, in the case of having only a single value, this value represents delay value, r-limit and e-limit. r-limit and e-limit are the lowest allowable pulse widths, i.e., any pulse narrower than r-limit will be rejected (no pulse appears on the port) and any pulse narrower than e-limit will appear as the X value.

Each of these three values (delay value, r-limit, and e-limit) can be a single or a triple value. The triple values that are separated by colons represent minimum, typical, and maximum values computed at three different operating conditions of a design. Line 45 of Figure 95.1 represent min:typical:max r-limits and e-limits for the rise and fall transition delays (of a 2-valued list). In this construct rise delay, rise r-limit and rise e-limit values are specified by the first three triples, i.e., 0.02:0.03:0.04, 0.01:0.02:0.03, and 0.02:0.03:0.04, while fall delay, fall r-limit, and fall e-limit values are represented by the last three triples (line 46), respectively, i.e., 0.03:0.04:0.05, 0.02:0.03:0.04, and 0.03:0.04:0.05.

Timing Specifications.

As discussed above, there are four types of timing specifications for each cell that are identified by DELAY, TIMINGCHECK, TIMINGENV, and LABEL keywords representing delay, timing check, timing envi- ronment, and label, respectively. Delay and timing check specifications are used for back annotation while timing environment specification is used for forward annotation. Labels represent timing constants used for annotating behavioral timing or readability purposes.

Delays — The delay type of timing specification that is used for back annotation starts with DELAY keyword and identifies the delay values of interconnects, input ports, input to output paths, and device outputs. Delays can be classified into four different groups: ABSOLUTE, INCREMENT, PATH- PULSE, and PATHPULSEPERCENT.

Absolute (increment) delays specify delay values that replace (increment) the existing delay values in a design. PathPulse and PathPulsePercent represent the absolute and relative values of pulse propagation limits between an input and an output port of a device. These types of delays specify whether a pulse on an output port of a device is rejected, filtered to X, or remains unchanged.

Absolute and increment delays are described by IOPATH, RETAIN, COND, CONDELSE, PORT, INTERCONNECT, NET, and DEVICE constructs.

• IOPATH delay: The input–output delay introduces the delay from an input/bidirectional port to an output/bidirectional port of a device.

• RETAIN delay: Retain delay represents the time duration in which an output/bidirectional port remains unchanged after a change in the corresponding input/bidirectional port.

• CONDITIONAL delay: Conditional delay starts with the COND keyword. In this construct, the corresponding delay values are applied to the related ports only if the introduced conditions are met.

• CONDELSE delay: Default delays can be specified for conditional paths using the CONDELSE structures. In this case, if the introduced conditions are not met, the specified delay in the CONDELSE structure is utilized by the annotator.

• PORT delay: Port delay represents the interconnect delay of an input port.

• INTERCONNECT delay: Interconnect delay specifies the propagation delay of a net connecting an output/bidirectional port (driving module port) to an input/bidirectional port (driven module port).

• NET delay: Net delay represents the propagation delay from all sources to all loads of a net.

• DEVICE delay: Device delay specifies the delay of all paths through a cell to a specified output port. If the output port is not specified, then the device delay represents the delay of all paths through a cell to all output ports of that cell.

Figure 95.2(a) and Figure 95.2(b) show an example design and its corresponding SDF file. Timing check constructs of this SDF file are discussed in the following section.

Timing Checks — The timing check timing specification, which is used for back annotation, starts with the TIMINGCHECK keyword and identifies timing check limits for a cell instance. There are 11 different types of timing checks that are discussed below.

• SETUP (HOLD) timing check: Setup (hold) timing check represents the time interval during which a specified signal must remain unchanged before (after) another signal transition.

• RECOVERY timing check: Recovery timing check introduces the minimum required time for active transition of clock after the release of an asynchronous control signal from the active state.

• REMOVAL timing check: Removal timing check specifies the minimum required time for release of an asynchronous control signal from its active state after an active transition of clock.

• SETUPHOLD timing check: Setup–hold timing check represents both setup and hold timing limits in an entry.

• RECREM timing check: Recovery–removal timing check specifies both recovery and removal limits in an entry.

• SKEW (BIDIRECTSKEW) timing check: Skew (bidirectional skew) timing check introduces the maximum permitted unidirectional (bidirectional) delay between two signals.

• WIDTH timing check: Width timing check represents the minimum acceptable pulse width of a specified signal.

• PERIOD timing check: Period timing check specifies the minimum allowable pulse period of a specified signal.

• NOCHANGE timing check: No-change timing check describes the minimum time for a specified signal to be stable before the start and after the completion of a control pulse.

A condition can be associated with all types of the discussed timing checks. For this purpose, the COND keyword is used and precedes the corresponding condition. The following is an example of a conditional setup timing check. In this example setup time between din and positive edge of clk is checked only when enable is active.

(SETUP din (COND enable (posedge clk)) (2))

Two other forms of condition are SCOND and CCOND. In multiple signal timing checks, SCOND applies to the first signal that changes, while CCOND applies to the second. In the following example, the condition is applied to signal clk for setup check and to signal din for hold check.

(SETUPHOLD din (posedge clk) (2) (3) (CCOND enable))

Figure 95.2(b) shows a number of timing check constructs to specify timing check limits for the cell instances.

Timing Environment — The timing environment type of timing specification, used for forward annotation, starts with the TIMINGENV keyword and represents constraint values of critical paths in a design. This construct also specifies the timing information of the design’s operating environment. There are two forms of timing environment specification. The first form represents constraint values for the design, while the second deals with the information about the timing environment in which the circuit operates. These constructs are described below.

Constructs for representing constraints include path, period, sum, diff, and skew constraints that are described below. Several of these constructs are used in the example of Figure 95.3(b).

• PATH constraint: The path constraint represents the maximum permitted delay of a path. A path is specified by its two ending ports. However, to unify the path, an intermediate port in the path can also be specified.

• PERIOD constraint: This constraint is used to introduce a path constraint value for a group of paths in a synchronous circuit. These paths lie between a common clock of several flip- flops and their related outputs. The starting point of all these paths is introduced by an output port of a device that drives the clocks of these flip-flops. Only flip-flops whose clock input is connected to this driving port directly or via a number of buffers are considered in the related period constraint structure. To be able to exclude a number of paths from the path group in this structure, an optional exception construct can be used. This construct starts with the EXCEPTION keyword and identifies the cell instances to be excluded from the path group.

• SUM constraint: The sum constraint includes two or more paths in a design and specifies the maximum allowable value for the sum of their related delays.

• DIFF constraint: This constraint includes two paths in a design and specifies the maximum allowable value for the absolute difference of their related delays.

• SKEW constraint: The skew constraint represents the maximum acceptable delay from a common driver to all driven inputs. These inputs must be driven directly by the common driver. In this constraint, only the driver port is specified.

As discussed above, the second form of timing environment constructs deal with information about the timing environment in which a circuit operates. These constructs are discussed below. Of what follows the waveform timing environment construct is used in the example of Figure 95.3(b).

• ARRIVAL time: The arrival time construct specifies the time in which a transition occurs on a primary input of a design. In this construct the primary input port along with four related values are presented. These values define the earliest rising, latest rising, earliest falling, and latest falling arrival times, respectively. In addition to these fields, another port edge can be specified in this construct. This port edge is considered as the time reference for arrival time specifications.

• DEPARTURE time: The departure time construct represents the time in which a transition occurs on a primary output of a design. The structure of this construct is the same as that of the arrival time construct.

• SLACK time: The slack time construct represents the maximum value that a path delay can vary without violating any design constraints. This construct includes a specified port along with four related values. To avoid specifying different paths in this structure, slack time structure considers all paths ending at the specified port. The four values in this construct are rising setup, falling setup, rising hold, and falling hold slack, respectively. Rising (falling) setup slack specifies the additional delay that can be tolerated by a design when there is a rising (falling) transition at the specified port. On the other hand, rising (falling) hold slack represents the reduction of delay that can be tolerated by a design when there is a rising (falling) transition at the specified port. An optional real number can be added to this construct to show the clock period on which the slack values are based.

• WAVEFORM time: The waveform construct introduces the specification of a waveform applied to a primary input of a circuit during its normal operation (see Figure 95.3(b) for an example). This structure includes the primary input port to which the waveform is applied, the period of the waveform, and its transition times during a given period. The transition times are specified by one or two pairs of transitions. Each pair consists of two edges: a positive edge followed by a negative edge or a negative edge followed by a positive edge. In the case of having two pairs of transitions, the order of edges in both pairs must be the same. Each edge is followed by one or two real numbers. If one real number is used, then this number defines the transition time and if two real numbers are used, they can define an uncertainty region in which the transition can occur (ambiguity area).

Figure 95.3(a) shows a circuit and Figure 95.3(b) shows a part of its corresponding SDF file including a number of timing environment constructs. As shown in Figure 95.3(a), in each clock cycle the input signal values are added/subtracted to/from the contents of the registers. Let us assume that we are driving this circuit with a clock of 500 MHZ. Thus the propagation delay from primary input signals to register inputs (i1 of Xo1 to o1 of AS1 and i1 of Xo2 to o2 of AS1) must be less than 2 ns (1/500 MHZ). Lines 19 and 20 of Figure 95.3(b) illustrate this constraint.

Labels — Labels represent timing constants used for annotating behavioral timing or read- ability purposes. Using label constructs improves the annotation performance, since labels can be looked up faster than port names and conditions. This type of timing specification starts with LABEL keyword and is classified into two different groups, ABSOLUTE and INCREMENT, each of which includes a list of delay values. Absolute (increment) labels specify delay values which replace (increment) the existing delay values in a design.

Our Coverage of SDF

The description of SDF presented here was an introduction to this format. We tried to cover the basics of SDF to familiarize the reader with the overall structure of this language and its applications. This section provided complete examples, and SDF structure, in the context of these examples, were described. Other language structures not covered by our examples follow the same basic patterns discussed here. This section did not elaborate on some of the constructs that were not covered in the above examples. For a complete description of this language readers are encouraged to see the references at the end of this chapter [1,2].

Related to the SDF format which describes timing of hardware components is the VCD waveform format. This format describes waveforms of circuit signals and is used for displaying data and for moving data across various platforms. VCD, including its timing representation is described in the section that follows.