ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN:SPECIAL LOGIC CELLS
SPECIAL LOGIC CELLS
Datapath Library Cells
The easiest way to understand what is datapath functionality is to consider the operation of an example circuit such as an arithmetic logic unit (ALU). The ALU is one of the three essential components of a microprocessor, the other two being data registers and the control circuitry. The ALU performs addition and subtraction, logic operations, masking, and shifting (multiplication and division) on multiple bits (signals) of data. An ALU is implemented in a datapath style.
As the name implies, a multiplier is a circuit whose output state is the arithmetic product of two input signals. This is another example of a circuit that is implemented in a data path style.
What are the characteristics of data path cells that distinguish them from standard cells?
• Signal flow: Typically, there are signals or bits of data flowing through the circuit, as you might imagine through an ALU or multiplier.
• Multiple signals: Several groups or buses of signals are flowing through the circuit at the same time.
• Requirement for symmetry: As the signals race through the datapath, it is highly desirable that each signal path be topologically identical to the others. This ensures that mismatches in timing do not occur and that the pre- dictability of each signal relative to each other is known.
How do we attack these special requirements in a systematic and efficient way? The answer is to use datapath library cells and techniques.
Let’s consider an example design as shown in Figure 5.11. This example shows four 8-bit signals being processes through three different functions (labeled
F1, F2, F3) and producing two output buses O1 and O2. The control blocks C1, C2, and C3 control all 8 bits of the functions simultaneously.
One alternative in implementing this in layout is to floorplan the circuitry as shown in Figure 5.11. In this case the requirements of symmetrical signal performance between bits would be difficult to achieve.
Let’s apply proper datapath techniques.
The first and most important detail is that the layout cannot start without a full picture of the functionality of the entire block. The way the signal lines have to run over the bits, their number and position, and the number of vertical tracks needed for internal cell connectivity are details that depend 100 percent on the schematic connectivity and performance requirements. In this case the design engineer and the layout designer have to work closely; otherwise, the full-custom block will not meet all design requirements.
The first step in proper datapath design is to consider the circuitry on a bit-by-bit basis. This is shown in Figure 5.12. Note that this should apply to both the circuit and layout design processes.
Remembering that the control signals are common to all 8 bits simultaneously, we can now start to see how we might achieve symmetry across all 8 bits.
1. Divide the complete functionality into smaller cells. In this case F1, F2, and F3 should all be separate cells. Each function is implemented as a row in the floorplan.
2. Define the interface to these cells first without completing the internal layout.
This must include the internal and external routing requirements for the cells. Consider the number and layer for both the vertical and horizontal tracks and share routing channels wherever possible.
3. Fill in the internal layout of the cells.
4. Complete the entire datapath for one bit. It is a simple process to step and repeat the layout for the rest of the bits. The cells should be designed to abut to themselves in the direction of the multiple bits.
Note that the schematic hierarchy and layout hierarchy should match for simpler verification and extraction. In our example, the floorplan of the layout will look similar to the flow shown in Figure 5.12 with the three functions imple- mented as cells and placed in the order shown.
Shared circuitry across all bits, such as the control circuits, should be considered in determining the cell breakdown and included in the floorplan.
Figure 5.13 shows an example interface design for one function for one bit of the datapath. This is considered to be one of the datapath library cells.
We can observe from Figure 5.13 that a datapath cell has many interesting features:
• The vertical cell interface starts and finishes with VSS power lines to allow abutment
• There are predefined vertical routing tracks for interconnectivity between the rows (functions)
• Signals can bend or jog over the cell when passing from one function to another as long as the signal exits on a predefined routing track
Figure 5.14 shows a complete implementation of a datapath circuit. Looking at the basic cell and the array of 3 functions ¥ 3 bits, we can observe the following:
• Internal cell routing is shown and is done based on available tracks. Signals run freely and vias are placed centered to the lines or offset from center.
• As the picture shows, there are many unused lines connecting different rows.
This was done intentionally to allow enough spare tracks for internal connectivity of the cells.
• All the routing is done for 1 bit only, and then the routing cell is arrayed over the width of the datapath.
• The rule of signal direction is respected here, too: M1 and M3 run only horizontally, M2 and M4 only vertically.
• All the gates generating the control signals are placed at the end of the row for each function. Routing tracks and efficient use of layout area are achieved this way.
• The end cells close off the substrate connections and overlap rules (for example, for N-well guard rings). Logic can be placed at both ends as required.
Because of the complexity of this layout, the color CD-ROM version of these diagrams may be easier to analyze.
A few comments about automatically place-and-routed datapath blocks. There are two kinds of datapath automation. One is a simple P&R of standard cells using a normal library and timing-driven limitations. The more advanced way to generate datapath blocks is using a specially built library with all the cells obeying the rules explained earlier. There are datapath-specific place-and-route tools that specialize in “bit” placement and routing and total symmetry of the signals in the bus.
Clock Generator Cells
Clock generator or perhaps clock buffer cells are generally special cells in a library. These cells are used specifically to buffer or amplify a very heavily loaded signal— namely, a system or chip clock signal. The system clock needs to be distributed all around the chip with as little delay as possible, and thus the implementation
What is so special about clock generator cells? The transistor sizes can be immense: 1,500 to 2,000 mm for a single device width is not uncommon. Compare these values to a minimum size inverter that can be 1.5 mm or so in width. To be implemented effectively, these huge transistors merit special layout techniques. The main concerns with such devices include the following:
• Optimizing signal and power connections in terms of resistance and capacitance.
• Healthy substrate connections—remember also that the clock in a chip is generally one of the highest speed signals and may generate a significant amount of noise and coupling into the substrate. Generally these transistors are isolated with independent guard rings.
• Techniques to reduce supply resistance include busing wide connections from power supply pads and a large number of vias.
• Electromigration rules must be strictly followed.
• The timing characteristics of clock signals are critical, so extraction and simulation of the layout is a must.
• If there are different clocks that need to be synchronized, then the layout should be symmetrical between them. A common technique is to use one clock cell that is configurable as it is used in different locations.
Please refer to Chapter 7 for a detailed discussion of the layout techniques for larger transistors, as well as to the pictures on the CD-ROM for a clock generator cell example. The picture is simply too complicated to show in black and white.
Bus Interface Unit (BIU) Cells or a Barrel Shifter
In complicated chips, there are many buses of signals that are helping the various blocks to interface in, within, or with the external world. Nevertheless, many buses and many signals are taking precious space from the chip area. Various blocks are working based on different clocks, so the solution was to develop switches for these buses in such a way that they can be used at different times by different blocks.
A bus interface unit, or BIU, is one of the solutions to control the traffic of signals over one bus at different times. Different signals are essentially multiplexed onto a common bus at different times. As such, these bus lines can be heavily loaded with mixing circuitry, and it is highly desirable to minimize the chip area consumed by purely routing channels.
There are some challenges in meeting these requirements:
• Minimizing the bus capacitance
• Minimizing the area consumed by the bus itself and the muxing circuitry
• Achieving symmetrical and predictable performance for all connections to the bus
An approach that minimizes signal capacitance and maximizes the use of the routing area is to plan for and implement this specialized circuitry directly under the signal routing. Parasitic loads for each of the numerous connections to the bus are minimized in this approach, and if a common cell is used, then all connections to the bus will be similar.
In terms of layout design, layout implemented directly under a signal bus is one of the most challenging tasks. Only experienced designers in full-custom layout are able to achieve quality results. All aspects of layout design must be considered and juggled when implementing this type of design—for example, area, size, positioning, capacitance, resistance, symmetry, and layers to be used for routing.
The CD-ROMshows an example of this type of circuitry, as it is too complex for the final design features to be effectively communicated in black and white.
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