THE MOS TRANSISTOR: THE BASIC CIRCUIT STRUCTURE

You have been given or have designed a schematic and are ready to move to layout. What’s next? In this chapter we will learn the basic building blocks of a schematic and the fundamentals of preparing yourself to implement the design in layout. We start by presenting the basic building block of all CMOS circuits— the transistor. We then continue by making sense of a typical schematic drawing, and we also lay the groundwork for more advanced topics.

THE MOS TRANSISTOR: THE BASIC CIRCUIT STRUCTURE

The transistor is the smallest building block or device that we need to understand to effectively implement or layout a design. Let’s first consider the functionality of the transistor and try to provide a basic understanding of the operation of a transistor so that we can maximize the performance of the design.

CMOS stands for complementary metal oxide semiconductor. This name is appropriate because there are two flavors of transistors, PMOS and NMOS, and together they complement each other, as we shall see in this section. Typically, a schematic might denote PMOS and NMOS transistors as shown in Figure 2.1. Note that the drain and source nodes are reversed as drawn in the diagrams.

In most cases the “Bulk” connection is always connected to the logical “1” level for PMOS and logical “0” level for NMOS. For this reason most schematics do

not show the bulk connection; it is implied. Of course, this is not always the case. For the moment, in the following schematics we will ignore the “bulk” connection.

The gates of the PMOS and NMOS transistors are open or the transistors are “on” under different conditions. PMOS transistors are “on” when the gate is at a logical “0” level. Conversely, the NMOS transistor is “on” when the gate node is at a logical “1” level. The way to remember this is that the bubble on the gate of the PMOS looks like a “0” and the NMOS gate looks like a “1” (Figure 2.2).

Both transistors operate very much like a “switch” or a valve in a water pipe. Like a valve, the “gate” controls whether the switch is open or closed. Positive current flow is defined as the action of “draining” water or charge from the drain side of the transistor to the water or “source” side when the gate is open. If the gate is closed, current (or water) does not flow.

A simpler way to visualize the operation of the transistors is as a resistor when it is “on” (Figure 2.3).

The amount of current that flows through the transistor is limited by the equivalent resistance of the transistor. As we shall see later, the sizing of the transistors directly affects this equivalent resistance. We will use this simpler resistor model in analyzing the operation of the transistors from this point on.

Now let’s consider the case when the source is connected to a static logic level. Generally, logical “1” levels are denoted on a schematic by the highest supply voltage for the design. Typically this high supply voltage would be labeled as VDD, VCC, or perhaps VPP. Conversely, logical “0” levels are denoted on a schematic by the ground level of the chip. VSS, GND, or GROUND are typical names. Under these conditions and with the gates of the transistors open the drain nodes are naturally driven to the same level as the source.

Due to the physical nature and limitations of the PMOS and NMOS devices (not to be discussed here), PMOS transistors are almost always used to establish logical “1” levels and NMOS logical “0” (Figure 2.4), although there are exceptions, of course. This is why PMOS and NMOS together have been termed “com- plementary”: they complement each other because, together, they simply and reliably generate both logic levels. For this reason, Boolean logic is easily implemented using PMOS and NMOS transistors, which is one of the main reasons why CMOS circuitry is so popular today.

Let’s not completely forget the bulk connection mentioned earlier in this section. Remember that the bulk is generally connected to the respective logic levels, and the implied connections to the supply levels are shown in Figure 2.5.

The size of the transistor should also be identified on the schematic (Figure 2.6). Each PMOS and NMOS has a length and a width. These dimensions will be

explained in detail in a later chapter, and for now take this as a given. Typically the length of either transistor may not be shown and has a default value. This value is usually the minimum allowable as limited by the process technology, and it is this number that is quoted to specify the technology. For example, a 0.25-mm process typically means the default gate length is 0.25 mm and thus is not shown on the schematic because it is redundant information.

In Figure 2.6 the width of the PMOS transistor is 5 mm, and that of the NMOS is 10 mm. Generally, the width value is always stated first. The PMOS transistor length is 0.5 mm, and since the NMOS is not shown, it is assumed to be the default value for the process, which is 0.25 mm.

When we start to look at the layout of transistors, it should become more obvious that the resistance of the transistor will decrease and the current drive of the transistor will increase as the width of the transistor is increased or the length of the transistor is decreased. For this chapter, please take this as a given.