SCHEMATIC FUNDAMENTALS:TRANSMISSION GATES

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TRANSMISSION GATES

Let us consider one more configuration of transistors that may appear in a schematic.

In the case of the inverter, the source of both transistors is connected to a power supply. In the case of combination gates, series connected transistors form part of a chain that eventually connects to a power supply, and thus the transistors should be treated similarly to the simple inverter.

The transmission gate is a fairly common case where both the drain and source nodes are used as signals. In this case, the output generally follows the input based on the state of the controls A and B. Note that this configuration allows for noninverting propagation of the input signal, as well as the blocking of the input signal when both control signals disable the PMOS and NMOS transistors. These are powerful features of this gate; transmission gates are used quite frequently and need to be designed carefully (Figure 2.16).

Remember we said that in general PMOS transistors are connected to generate logical “1” levels and NMOS logical “0,” and almost never the reverse. The truth table for the transmission gate shows one of the reasons why this is so. PMOS transistors are able to pass “0” levels, but they do so somewhat unwillingly and degrade the “0” level. The same is true for NMOS transistors and “1” levels. This is what is meant by “Weak Levels” in the truth table. Unless specifically intended, these weak-level conditions are generally avoided in robust logic designs. Usually both controls are implemented such that the transmission gate is either completely “on” or “off” (both transistors) but not halfway.

Schematic Fundamentals-0009

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