LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS:SPECIAL DESIGN RULES

SPECIAL DESIGN RULES

In previous chapters we learned the basics about process order flow and design rules related to process and circuit requirements. However, there are a few interesting exceptions to “general” design rules.

We cannot explain in detail all the “weird” rules related to specific types of processes. Our intent is to increase the reader’s awareness of some process-related issues that are not always described from the beginning in the design rule sets. In general, it makes sense to talk to the process people to understand the technical reason behind any special design rules and try to work with them to determine practical solutions.

Minimum Area Rule

A rule that becomes more prevalent as geometry get smaller is the “minimum area” layer rule. Although design rules such as transistor gate length are shrinking, not all of the many layers in the manufacturing process shrink equally.

One example of this is the definition of active areas, especially for small poly- gons. This limitation is typically specified as a minimum width and area rule. Small active rectangles can occur quite frequently for substrate connections that are made with a single contact between metal1 and active. In this case, if only the minimum width rule is followed for the length and width of the polygon, an active polygon may result that is smaller than what can be produced.

Adding length to a polygon is an easy solution to conform to the “minimum area” rule. See Figure 8.10 for example layouts illustrating this rule.

End Overlap Rule

We learned about a generic contact overlap rule in Chapter 3, but in some processes this rule is enhanced by a rule known as the “end overlap” rule.

This rule applies when a contact is located at the very end of a line. The problem that this rule addresses is shown in Figure 8.11 by the dashed lines denoted as “Shape on Silicon.” Contacts that are placed at the very end of a line are in danger of not being filled as the metal is rounded in real silicon. This danger is increased if any amount of misalignment occurs during processing.

Double Contacts

Consider once again DRAM processes where the limits of the manufacturing process are consistently tested in order to achieve a small memory cell. In this case the overall reliability of many standard structures is in question for many design rules.

Outside of the memory array, where the topology of the layout is not regular, more stringent design rules are enforced. One of these is the requirement for double contact and vias for every connection. This rule applies to transistor layout and general routing and signal connections.

The double contact and/or double via not only improves the resistance of the connection; more importantly, it provides added reliability by having redundant contacts for every connection.

A problem with this requirement is that placing double contacts using automatic tools is a challenge for place-and-route tools. These tools prefer square via/contact cuts (cells). Connections are easily made in both X and Y directions, and the tool does not have to orient the contact or via cell during placement.

Figure 8.12 shows two equivalent layout designs, one with single cut cells and the other with two. As we can see from the example, such layout styles increase chip size and the amount of work required to design a memory chip. For the present, DRAM layout designers can get very little help from the automation.