ADVANCED TECHNIQUES FOR BUILDING-BLOCK INTERCONNECT LAYOUT DESIGN:CLOCK SIGNALS

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CLOCK SIGNALS

Typically in every design most blocks are synchronized to operate from one central global clock signal. The global clock signal usually is second only to the power supply signals in terms of its need to be routed all over the chip.

For this reason, it is important and efficient to plan for the clock signal after the power supply routing and before routing the rest. Once again, inserting a clock signal into a completed design is difficult and should be avoided.

Fundamentally, the goal of implementing a clock signal is to distribute a single signal around a large area with minimum delay. The clock signal has a large capacitive load; therefore, in order to minimize the delay, many different approaches are used.

The global clock is typically generated either directly from the pad or from an internal clock generator cell. Considerations for the layout design of the clock generator cell include the following:

Advanced Techniques for Building-Block Interconnect Layout Design-0094

• Placement: Ideally placed near the external clock pad as well as power supply pads. The clock generator itself is a large consumer of power; therefore, it is a source of power-supply noise. This noise should be isolated from the rest of the chip by connecting the generator to independent or power pads that are nearby.

• Buffer stage design: As discussed in Chapter 5, the clock buffer cells can be extremely large (thousands of microns in transistor width). Each stage in the buffer chain should be designed to minimize the area and power consumption. The transistors are laid out using special methodologies for reduced power connection resistance, minimum input capacitance on the gates and most importantly minimum output capacitance.

Single Clock Signal

One option in implementing a global clock signal is to run a single interconnect line that originates from the clock generator.

In this case techniques similar to the ones presented in Section 6.1.2 should be used. A routing approach such as the “root” or “resistance” approach is valid.

Capacitance effects are more important in this case because the clock signal is a dynamic signal. The choice of routing layer should be made to reduce both the resistance and capacitance of the line.

Shielding of the clock line is useful to isolate other signals from the clock signal and to reduce the coupling capacitance of the clock signal.

Clock Tree

Another very common type of clock implementation scheme is called a clock tree. It is most common in an ASIC style of design, as the automation of generating a clock tree fits easily into the ASIC design flow.

A clock tree is a network of buffers inserted into the clock signal path in such a way that the overall delay from the generator to all destinations is minimized. Instead of one electrical signal path being optimized, the path is broken up and strategically buffered to minimize the delay. The resulting network resembles a tree in that the central clock signal branches throughout the chip using these buffers and ends up with the clock signal reaching all of the leaf cells.

Typically, the steps in implementing a clock tree are as follows:

1. An initial placement of the logic cells is completed. This ensures that the timing performance of the core logic is met.

2. The clock tree is inserted, taking into account the location of the logic cells.

The buffer cells are placed or inserted in strategic places to minimize the clock delay and routing.

3. The routing is completed for all signals and optimized to meet all timing goals.

Automatic tools in an ASIC flow are available; however, the same procedure should be used in any design.

In principle, to design a clock tree a designer should consider the following:

• First define/understand the scope or extent of the clock tree. This would include items such as the total load, routing area, distance the clock has to travel, available routing layers, and routing restrictions.

• Define the constraints that the clock tree must satisfy, including minimum and maximum insertion delay and maximum skew.

• Define the way the clock tree topology will be generated, including number of levels or buffer stages in the tree and the type of buffers/inverters and fanout limits at each level. The topology can be defined manually by the designer, or automatically by a clock tree generator tool.

Figure 6.3 shows two examples of clock trees.

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