Multidimensional Logarithmic Number System:Extending to More Bases

Extending to More Bases

The conversion methods shown here can be easily extended into MDLNS representations with more than 2 bases (assuming one of the bases is still 2). Since all the methods shown rely only on information about the mantissa and exponent, multiple bases can be merged, generating a single mantissa and exponent. For example, Table 84.9 shows an MDLNS-to-binary conversion LUT using bases 2, 3, and 5, and a word length of 2 bits for the indices using bases 3 and 5. The nonbase 2 indices can be combined through

simple word concatenation to generate a single word that can address the table to determine the proper mantissa and exponent.

This same approach can be used to generate the RALUTs for binary-to-MDLNS conversion. Similarly, the combined second base RALUT output can be easily separated to find the nonbase 2 indices to generate the MDLNS representation.

Binary to Two-Digit MDLNS (n > 2)

The methods used in single-digit and two-digit 2DLNS conversion can be extended to operate with an n-digit 2DLNS with n > 2. The two methods are briefly reviewed below for completeness, although some implementations can become impractical as n increases.

Quick Method

The quick binary-to-two-digit 2DLNS conversion process can be easily extended into an n-digit system. The serial implementation of the n-digit conversion requires extra states in the controlling state machine to produce approximations for the remaining digits. The output latency is a multiple of n, but the bandwidth decreases. The parallel implementation requires additional pipeline stages (normalizers and RALUTs) to meet the n-digit specifications. The latency is n cycles, but maintains its operating bandwidth.

High/Low Method

The High/Low method of conversion does not scale as well as the Quick method since there are many possibilities to consider when converting from binary into 2DLNS. For the serial implementation a stack- based state machine is used to traverse all the possible representations for the n-digit 2DLNS representation to find the best representation [22]. The parallel implementation requires double the number of conversion components for each pipeline stage from the previous stage (i.e., 1, 2, 4, 8, 16, ¼). In total, 2n - 1 conversion components will be needed. Just as in the Quick method, the latency will increase, but the bandwidth will remain the same. The final stage will require 2n-1 -1 comparators to determine the best n-digit 2DLNS approximation (see Figure 84.10).