Multidimensional Logarithmic Number System:Extending to More Bases

By -
Extending to More Bases

The conversion methods shown here can be easily extended into MDLNS representations with more than 2 bases (assuming one of the bases is still 2). Since all the methods shown rely only on information about the mantissa and exponent, multiple bases can be merged, generating a single mantissa and exponent. For example, Table 84.9 shows an MDLNS-to-binary conversion LUT using bases 2, 3, and 5, and a word length of 2 bits for the indices using bases 3 and 5. The nonbase 2 indices can be combined through

Multidimensional Logarithmic Number System-0185

Multidimensional Logarithmic Number System-0186

simple word concatenation to generate a single word that can address the table to determine the proper mantissa and exponent.

This same approach can be used to generate the RALUTs for binary-to-MDLNS conversion. Similarly, the combined second base RALUT output can be easily separated to find the nonbase 2 indices to generate the MDLNS representation.

Binary to Two-Digit MDLNS (n > 2)

The methods used in single-digit and two-digit 2DLNS conversion can be extended to operate with an n-digit 2DLNS with n > 2. The two methods are briefly reviewed below for completeness, although some implementations can become impractical as n increases.

Quick Method

The quick binary-to-two-digit 2DLNS conversion process can be easily extended into an n-digit system. The serial implementation of the n-digit conversion requires extra states in the controlling state machine to produce approximations for the remaining digits. The output latency is a multiple of n, but the bandwidth decreases. The parallel implementation requires additional pipeline stages (normalizers and RALUTs) to meet the n-digit specifications. The latency is n cycles, but maintains its operating bandwidth.

High/Low Method

The High/Low method of conversion does not scale as well as the Quick method since there are many possibilities to consider when converting from binary into 2DLNS. For the serial implementation a stack- based state machine is used to traverse all the possible representations for the n-digit 2DLNS representation to find the best representation [22]. The parallel implementation requires double the number of conversion components for each pipeline stage from the previous stage (i.e., 1, 2, 4, 8, 16, ¼). In total, 2n - 1 conversion components will be needed. Just as in the Quick method, the latency will increase, but the bandwidth will remain the same. The final stage will require 2n-1 -1 comparators to determine the best n-digit 2DLNS approximation (see Figure 84.10).

Comments

Post a Comment

Popular posts from this blog

Square wave oscillators and Op-amp square wave oscillator.

By -
Image
Square wave oscillators If Fourier analysis is performed on a square wave it is found that the waveform is composed of many harmonics of the fundamental frequency. This rich harmonic content makes the square wave particularly useful as a quick test of amplifier performance. Examples of possible results are shown. The simplest way to produce a square wave is to make a sine wave oscillator in one of the ways described earlier, then feed the output to some form of squaring circuit such as a Schmitt trigger. This is the method adopted in most commercial sine/square wave generators. There are, however, several circuits for square wave oscillators and a description of the most common follows. Multivibrator Technically the multivibrator is a relaxation oscillator, working on the charging of a capacitor through a resistor. If a negative edge is applied to the circuit in (a), transistor TR 1 turns off the for time taken for the base voltage to return to 0 V. If the voltage step is...
Read more

Adders:Carry Look-Ahead Adder.

By -
Image
Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher...
Read more