LAYOUT DESIGN FLOWS:CAD TOOLS AS PART OF A FLOW

CAD TOOLS AS PART OF A FLOW

Each step in a ﬂow is usually based around a speciﬁc CAD tool to perform the required operation. The choice or understanding of a tool within any ﬂow depends on many factors, and it is these factors that we will discuss in this section.

The ﬁrst concept to understand is that fundamentally all CAD tools fall into one of these two categories:

• Design entry: Methodology to implement the idea into a useable form with all the desired characteristics

• Design validation: Methodology to analyze and verify that the design has been entered correctly (i.e., it functions appropriately, performs as required, and is manufacturable)

Different tools address these two requirements in different ways or may address different issues. It is these different approaches that have spawned an entire industry in which each vendor tries to ﬁnd the magic formula to develop the most effective design ﬂow.

Over time, the number of tools to choose and understand has dramatically increased because there has been a tremendous growth in the variety of the following:

1. Design types: For example, the ﬂow for a microprocessor design differs greatly from that for an analog component; therefore, a different set of tools is used. In this example there are design size and complexity differences to manage as well, which necessitates a different ﬂow between them.

2. Capture techniques: Certain tools operate at different levels of abstraction in order to enable designers to capture their design ideas more efﬁciently. The difference between ﬂoor planners and polygon editors demonstrates this concept. They are both layout entry tools, but they capture design ideas at the block level (ﬂoor planners) or the transistor level (polygon editors).

There are different capture techniques in the circuit entry domain as well. Schematic capture is one type; use of an HDL (high-level description language, usually VHDL or Verilog) is another. Schematic design captures a design at the transistor level; use of an HDL captures a design at the RTL (register transfer level).

The difference between these two types of circuit entry has great impact on the layout design, as there are signiﬁcant differences in the database format, size, and complexity of the resulting circuit design. An RTL-based design may result in anywhere up to millions of instances to layout. The ﬂow for this design will be quite different from schematic-based ﬂow, which produces much smaller designs.

3. Design size and complexity: One category of tools is one that automates tasks that would be logistically impossible for a designer to complete by manual techniques. Place-and-route tools that can implement millions of instances are examples of automation tools in this category.

4. Degrees of specialization: Each tool focuses on solving or addressing a small number of the required characteristics for a layout design. For example, the steps of routing signal lines within blocks and doing the same between blocks are often separate and use different tools, as they each have different requirements or constraints that cannot be covered by one tool.

It is likely that there are separate tools available for each of the characteristics listed in Table 4.1, thus leading to a complicated ﬂow for sophisticated designers who need to address all of these issues.

5. Interface points: There has been a signiﬁcant trend toward having feedforward and feedback loops in the design ﬂow. This has increased the number of interface points for each step in the ﬂow. For example, ﬂoorplanners give interface information to other layout tools as well as to circuit veriﬁcation tools. Layout editors must also be able to feed their results back to the ﬂoor- planning tool as well.

Circuit design information should be ﬂowing from the circuit designers forward to layout (as constraints or goals), and the results of layout at each step should be fed back to the circuit designers for veriﬁcation. If this information is transferred more often and to greater levels of accuracy, then the overall design process will produce a much better result.

6. Accuracy requirements: Design tools have had to increase their abilities and accuracy to be able to implement new process technologies. Extraction tools have increased in accuracy, with examples such as 3D ﬁeld solving techniques for near-body capacitance calculations.

7. Acceleration techniques: Often an existing step in the ﬂow can be accelerated using a new tool that approaches the problem in a novel way. The functionality of the step is unchanged, but the algorithm in the tool accelerates the process. An example is the emergence of hierarchical layout veriﬁcation that is many orders of magnitude faster than the previous ﬂat hierarchy approach and provides identical functionality.

8. Database formats: Some companies develop proprietary database formats for their tools. These companies also develop tools of equivalent functionality to those already available in order to provide designers the complete capa- bilities they need using the proprietary database formats. Alternatively, they develop translators that interface other database formats to theirs.

There are also issues with database compatibility for the case when circuitry to be implemented has come from a previous design or from a third- party supplier. In some cases, leveraging the experience of others through reuse or block-based design may affect the choice of tools in the ﬂow. Typically, tools and/or steps in the ﬂow are added to verify and translate the circuitry so that it is compatible with the current set of tools in the ﬂow.

Using speciﬁc examples, the remainder of this chapter concentrates on the impact to the ﬂow of the different design types that are common today. The type of design usually deﬁnes the tool set, mainly because the design size and complexity dictates the tool set that will accomplish the design in a reasonable amount of time. These examples will demonstrate the concepts we have presented in order to help you understand the appropriate set of tools for a speciﬁc design type.

Analog IC Design Flow

The greatest number of ICs shipped today fall into this category of products. The functions of analog ICs range from single transistor devices to complex functions that are characterized by very precise operating characteristics. Operational ampliﬁers, converters, and phase-lock loops are only a very small sample of these device types.

These devices are designed to exhibit extremely accurate analog characteristics. Output voltage levels and power consumption are very carefully controlled. Extremely detailed control of the manufacturing process is required because the circuitry on the chip is very sensitive to small variations of the transistor characteristics. Yield and reliability issues are examined more thoroughly than other device types because a large number of devices are produced. Table 4.2 summarizes key characteristics that are of most concern in the design of analog ICs.

Typically, understanding and capturing the fundamental behavior of the circuitry is straightforward. A small proportion of the circuit designer’s time is spent to verify that the behavior of the design has been captured correctly. Compared to other design types, the number of transistors within the design is very small.

What type of ﬂow is used to design this type of IC?

The answer is that it is probably one of the oldest design ﬂows that exists unchanged today. At one time all IC design was done using the fundamental ﬂow presented here.

This type of ﬂow is generally known as a “full-custom” design ﬂow (Figure 4.3), a term that comes from the freedom to completely customize all aspects of

the design. Transistor sizes and the layout implementation are both carefully designed to ensure that the ﬁnal design will perform as intended.

The ﬂow shown in Figure 4.3 is straightforward. From the speciﬁcation, the circuit is entered and validated. Once complete, the layout is implemented, veriﬁed, and, as a ﬁnal step, extracted and resimulated to ensure that the physical implementation operates as designed.

The circuit entry step is known as schematic capture, where transistors and customizable logic gates are entered as the implementation of the design. Components are manually selected, placed, and connected. The graphical look of the schematic is purely aesthetic from a ﬂow point of view, but an understandable schematic is crucial for the design team to develop, communicate, and debug the circuit implementation of the design.

The layout is captured as polygons or paths. A polygon editor is used to capture and draw each individual transistor. Very detailed knowledge of the manufacturing process and the relationship between layers is required at this level of layout. It is also very important that the impact of different layout implementa- tions on circuit performance be fully understood.

The schematic capture and polygon editing tools form the foundation of the full-custom design ﬂow. These tools are primarily used in the role of capturing a useable representation of the idea as stated in our deﬁnition of a ﬂow.

Automating this type of ﬂow is difﬁcult because the main issues that the design team needs to address are not easily solved using existing CAD tools. Issues such as noise immunity, reliability, and yield are left to the design team to evaluate once the layout is complete. The circuit validation process typically includes a large amount of visual inspection of waveform databases from detailed simulation models.

As such, the bulk of the analysis to determine whether or not the design exhibits the appropriate characteristics for its intended use is a labor-intensive affair requiring expertise in transistor operation and the physical characteristics of the manufacturing process.

In summary, analog circuit design demands the accuracy and control in implementation that a full-custom design ﬂow provides. This is because of the design’s requirement for very precise and stringent analog performance characteristics. Schematic capture and polygon editing are the fundamental tools of this ﬂow.

ASIC Design Flow

In the IC design industry, it is common to hear people say “The heart of our system is a complex ASIC” or “Our design was implemented in an ASIC style.” Companies advertise for people with “ASIC design skills.” This really means the company is looking for people who are familiar with the ASIC design ﬂow. It is the industry’s deﬁnition of an ASIC design ﬂow that will be described here.

In a strict sense, ASIC (application-speciﬁc integrated circuit) is a generic term that describes components that have been designed for a speciﬁc application and not as a multipurpose device.

For example, a telecommunications system could be designed using standard components such as counters, logic gates, and ﬂip-ﬂops. On the other hand, if an ASIC component was used, the counters and logic gates would be integrated on one IC and the function of the IC would only be useful in the system for which it was intended. In some cases these ASICs could be sold as a standard product to be used in multiple systems. This last example is normally referred to as an ASSP (application-speciﬁc standard product).

Theoretically, any ASIC could be implemented using the full-custom design ﬂow described in the previous section (or any other ﬂow, for that matter). In the IC design industry, however, the term ASIC has become far more synonymous with a certain design ﬂow than a design type, although the term ASIC is used in both contexts.

What is meant by an ASIC design ﬂow?

“Synthesis” and “Place-and-Route.” These two very common terms in our industry capture the essence of an ASIC design ﬂow. Their methodologies have revolutionized the way IC design is done today.

First let’s understand the underlying principles of this ﬂow, shown in Figure 4.4.

The following are some key points:

• Circuit entry: The design is implemented using a software language that is commonly known as RTL (register transfer level), but is in fact an HDL (high-level description language) written at the RTL level.

VHDL or Verilog are examples of HDL languages that are used to capture design information. These languages support many different constructs. The most common way of describing an idea using an HDL is to write the code at a level of abstraction called RTL. At this level of abstraction, the code can be automatically converted to logic gates and sequential elements such as ﬂip-ﬂops and latches. This process is generically known as synthesis.

• Layout entry: The logic gates and sequential elements produced by synthesis tools are automatically placed and automatically connected using a P&R (place-and-route) tool.

Note that P&R tools are designed to produce layout that is “correct by construction”; therefore, layout extraction for simulation is a step in the ﬂow before layout veriﬁcation. Layout veriﬁcation is always required as a ﬁnal step to ensure the integrity of the layout database and to check that any addi- tions or changes made after P&R are veriﬁed.

• Library of cells: A prerequisite to this ﬂow is the existence of a “library” of cells. The library consists of the logic gates and sequential elements that the synthesis and P&R tools use. In any design ﬂow that follows an ASIC ﬂow completely, the entire design is implemented using only the library cells and nothing else.

The ASIC design ﬂow is probably the most common design ﬂow these days, with the majority of ﬂow and tool development supporting this methodology.

In an industry where the level of technology advances very quickly and products become out-of-date within a few years, the primary business focus of successful companies is to produce new products very quickly and productively. Minimizing the time-to-market of any product is crucial.

In many ways the ASIC design ﬂow has enabled this revolution in productivity, especially when compared to the older full-custom design ﬂow.

In this ﬂow, circuit entry is simply “coding” and therefore is very quick and easy. A large amount of functionality can be captured in a very short time. It is easy to maintain and reuse, and it is not dependent on a particular manufacturing technology. These are all signiﬁcant beneﬁts.

The example of code shown in Figure 4.4 is VHDL code of a counter from 0 to 9 (2 minutes to enter at 25 words per minute). Drawing a schematic is much more time consuming. Imagine changing the counter to decrement from 100 to 0 in a schematic-based design (or in a full-custom layout ﬂow)!

This explosion of productivity on the circuit side has been matched for the layout-entry step by the development of P&R tools. Full-custom layout techniques are not practical when the circuit design is tens or hundreds of thousands of instances!

Advances in IC manufacturing processes have been one of the primary drivers of the development of all of the automation technology that forms the ASIC ﬂow. Available transistors on a single chip have increased dramatically over time.

The ability to use this increasing number of devices has been addressed by this ﬂow because the design process has been elevated to the logic-gate level, where logic functionality is the primary concern. The transistor level and many of the process-related issues are hidden within the library and modeled throughout the ASIC ﬂow.

Table 4.3 summarizes key characteristics that are of most concern in an ASIC design ﬂow.

Not only has this ﬂow increased the productivity of IC designers, but it has also attracted many people to the world of IC design. The circuit and layout designers are separated from the complexities of the process design rules because these rules are hidden in the library. The circuit designer worries only about implementing logical functions. The layout designer may get by with process knowledge related to routing layers only.

To recap, an ASIC design ﬂow is a speciﬁc design type using HDL coding, synthesis, and P&R methodologies to implement the design. In this case it is the use of a HDL for circuit entry that forms the foundation of the ASIC design ﬂow.

We can infer the many tools of an ASIC ﬂow. HDL circuit entry requires the following:

• Circuit veriﬁcation methodologies speciﬁc to HDL code

• The use of synthesis to implement the HDL design to logic gates

• Circuit veriﬁcation methodologies for the resulting large logic gate design

• Tools to feed forward circuit constraints such as groupings and timing constraints

• Tools to convert extracted layout data to relevant circuit veriﬁcation data

The size and complexity of the resulting design mandates the use of different layout-related tools from those for a full-custom design ﬂow:

• Floorplanning tools to group and guide placement of cells

• Automatic layout entry methods in the form of P&R

• High-capacity layout veriﬁcation and extraction tools for large designs

There are additional tools and methodologies to generate libraries:

• Characterization tools to produce models for synthesis and simulation

• Implementation of cells in layout using a full-custom ﬂow

• Alternatively, migration of cells from an existing library

• As another alternative, use of layout synthesis tools to generate library cells In summary, an ASIC design ﬂow is one that is most appropriate in implementing a complex and sizable logic design. HDL circuit entry, synthesis, and P&R tools are ideal for this type of design.

Memory IC Design Flows

Fast-page DRAM, cache, EDO DRAM, SRAM, and SDRAM are terms that should be familiar to anyone who has recently purchased a personal computer. The amount and type of memory in any personal computer is well advertised. We now understand that the more memory our computer has, the better and faster it will perform.

We are covering memory IC design in a separate section because it is a design type that is best implemented using a layout-ﬁrst design ﬂow. In terms of layout design, it is one of the few design ﬂows where the layout is implemented before the circuit design!

This can be explained by ﬁrst discussing the architecture of a memory IC. Figure 4.5 shows an example ﬂoorplan of a DRAM memory. Note that the majority of the chip area is consumed by the core memory cells and supporting circuitry.

The important concept to understand is that there are a relatively small number of leaf cells that are repeated literally millions of times. Any area savings that can be achieved for each leaf cell beneﬁts the area of the chip many times over.

The most important example of this is the memory cell itself. Memory manufacturing processes are unique in that they have been speciﬁcally designed to achieve a small memory cell size. In the case of memory cell design, the unit of measure is more often nanometers rather than microns.

Figure 4.6 shows a design ﬂow that is typically used in memory design. The following are some key points:

• For memories, the key design characteristics are area, area, and area. Memory ICs are commodity products, and extra area equates to extra cost.

The goal of a memory design is to pack a ﬁxed number of memory cells in the smallest die. The design team’s goal, therefore, is to minimize the area consumed by the periphery and nonmemory-cell circuitry. The ratio of memory cell area to the total die area is known as the cell efﬁciency of the design.

• As mentioned, the layout is done ﬁrst. Typically, the memory cell is developed in conjunction with process development so the layout of the memory cell may be provided.

• This memory cell forms the basis for an inside-out layout ﬂow. The memory core circuitry is built starting from the memory cell. The decoder and sense ampliﬁer cells are “pitch-limited” in that the pitch of the memory cell is a limiting dimension for these cells.

• The design ﬂow of the memory core pitch-limited circuitry is a very tight iteration loop between layout and circuit design. Many circuit design trade- offs are made to achieve a ﬁnal implementation that is area efﬁcient.

These design trade-offs could be architectural as well. For example, the number of decoders and sense ampliﬁers is carefully chosen to ensure that a reasonable cell efﬁciency is achieved.

• Once the architecture of a memory design is well deﬁned and validated, the architecture is often captured within a memory compiler or layout-tiling program for future use. Memories have a very regular structure and there- fore are easily programmed into an automatic process.

• The control logic of a memory is still generally done in a full-custom style to minimize the total area of the die. Schematic capture is typically used as the design capture methodology.

In summary, a memory IC design ﬂow is one where the area is the ﬁrst priority and therefore the layout characteristics are the key considerations during the chip’s development. Thus, the design of memories is one of the more interesting challenges in layout design.

Microprocessor and SOC Design Flows

These designs have the most complex and intricate design ﬂows and represent the state of the art in IC design. Microprocessor designs that are produced by companies such as Intel and Motorola combine all of the different ﬂows that we have discussed so far. SOC (system on a chip) is a generic name for ICs that integrate a wide variety of complex and diverse functions onto a single die. In both cases it is the performance and cost beneﬁts of a single chip solution to implement the required functionality that drives their development.

There is not one single design ﬂow for the chip, but a mix of full-custom, ASIC, and memory design ﬂows. There are variations of the three ﬂows as well, depending on the block under development.

The effort and expertise that go into these types of designs is staggering and typically spans multiple years. Simply examining a ﬂoorplan of one of these ICs makes clear the variety and complexity of these designs. Each major block is planned and implemented using the ﬂow most appropriate for its type. Once each block is complete, a separate ﬂow of assembling the blocks is done.

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