ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN:MEMORY DESIGN LEAF CELLS

MEMORY DESIGN LEAF CELLS

Memory layout design is a real challenge to a newcomer. The design of memory- related layout cells requires detailed knowledge of both the manufacturing technology and the circuit architecture and performance issues.

In most design styles, there are portions of memory such as SRAM, but the most challenging is the dynamic random access memory, or DRAM. Figure 5.21 shows a floorplan of one implementation of a DRAM core.

First we have to see how a basic memory cell looks in a circuit (Figure 5.22). This is because the manufacturing process is most complex, as shown in Figure 5.23.

The stacked capacitor DRAM memory cell has special layers that form the memory cell capacitor. Any DRAM memory cell layout is generally very process specific, and company confidential as well.

As Figure 5.23 shows, the DRAM memory cell is very high (tall) in terms of the manufacturing process. Generally the node and plate poly layers are allowed for use only in the memory cell area. The sense amplifiers therefore use at most only two poly layers, and the topology of this area is significantly lower. “Friendly” cells are used to interface the regular patterning of the memory cells

to the irregular patterns outside the memory cell matrix. It is an area where the vertical topology can be gradually decreased for areas outside the array. Shielding can also be provided by connecting layers in the friendly cells to quiet signals such as power supplies.

As we explained in Chapter 4, “Layout Design Flows,” the design of the memory has a very strong dependency on the layout. In fact, the layout of the memory is done first and the schematic design follows. The reason is simple: because the memory cell is repeated many, many times, it is crucial to minimize its size. From this base we build the rest of the circuitry around the matrix of memory cells. This leads us to the topic of pitch-limited layout.

Pitch-limited layout is a type of layout design where the cell under consideration is restricted in one dimension and must interface to a “leader.” The leader in most cases is a repeated cell like the memory cell of a memory array. All planning effort should be focused on minimizing the size in the unrestricted dimension.

Figure 5.24 shows an example of a memory core. In this case the WL (Word- line) Driver, Wordline Strap, and Sense Amplifier cells are examples of pitch- limited layout.

In analyzing the memory array shown in Figure 5.24, note that the pitch of the cells is not the same as in the memory cell. For example, the wordline driver cell has a pitch of two cells.

The pitch matching of cells is what makes this type of layout so challenging. Whenever there is a significant mismatch in the circuitry to be implemented between two cells, inevitably the follower cells are modified in many ways to meet the leader cell’s requirements.

Generally a leader cell has been highly optimized to implement a specialized circuit with minimum design rules. The result is that the dimensions of the cell are defined by a very specific number of rules.

Given these specific requirements, it is usually very unlikely that the pitch- limited cells around the leader cell can meet the same pitch. The follower cells will have different circuit requirements that will not match the critical design rules that limit the leader cell.

In the case of memory cells, it is not uncommon for the design rules to be different for the pitch-limited circuitry, since the topology is not as regular as that of the memory cells. These differences make the layout more challenging.

Subsequent sections will discuss examples of pitch-limited layout cells to illustrate the preceding concept. In all cases, it is the memory cell pitch that is limiting one dimension of these cells.

Wordline Strap Cells

In terms of the concept of pitch-limited layout, the wordline strap cell differs in topology from the leader cell by the addition of a contact between the poly and metal wordlines. The memory cell is built on almost an absolute minimum metal pitch without a contact, and it is at the strapping points that a contact is added. Therefore, in the wordline direction there is very little extra space to put contacts.

Why is this cell needed? The wordline strap cell is an interesting cell to understand because it is a purely layout solution to a circuit design problem, and there are many ways to implement it.

The wordline driver typically has a gate load of 1,024 memory cells. This gate load is a large capacitive load, and the resistance of the long line of gate poly makes the delay of the wordline prohibitive. The resistivity of a metal line is typically three or four orders of magnitude less than that of gate poly, so strapping the wordline regularly to reduce the wordline delay makes a lot of sense.

The frequency and placement of these straps should be determined primarily based on the polysilicon resistivity, wordline performance requirements, area, metal and contact resistance, symmetry between wordlines, and failure analysis concerns. Figure 5.25 shows different strapping schemes and the pros and cons of each.

These schemes assume that the frequency of the strapping has been deter- mined. The frequency of strapping is mainly determined by wordline performance requirements; however, the area impact of one strapping scheme may result in alternatives being considered.

In terms of the layout of a wordline strap itself, we have to deal with the fact that across the memory cells, the wordlines run in almost minimum pitch without a contact, and the task is to put contacts in for every line.

The solution is to stagger the contact cells. By analyzing Figure 5.26, we can understand how we can gain in the width of a bus connection.

Please check the CD-ROM for a color version of the wordline strap diagrams.

Wordline Driver

In comparison to the wordline strap, the wordline driver is a much more complicated cell. Instead of fitting a single contact in the pitch of a wordline, we need to implement an entire driver stage! This might be a CMOS inverter or an alter- native optimized specifically to minimize the area and performance requirements.

Describing the details of this process is beyond the scope of this book, but the fundamental approaches to this type of layout have been covered.

As we determined the required stagger in the wordline strap case, we generally do the same for the driver, except for transistor with interconnect staggering. Determining the minimum pitch of a transistor in a wordline driver environment has almost endless variations.

Here are some other things to consider or remember:

• Build the cells similarly to the datapath cell strategy, in that the neighbors of the cell are itself. Consider the wordline direction as the datapath direction. Use the direction perpendicular to the wordline for control lines.

• If the manufacturing process is immature or a new circuit is being implemented, most process engineers are willing to negotiate on some design rules when confronted with pitch-limited layout design. Typically, significant area penalties can be avoided, and there may be more tolerance in the design rules because the drivers are regular patterns and are close to the memory cell array where the processing is very well controlled.

• Be aware that DRAM memories have multiple power supplies such as a super voltage VPP and a negative substrate voltage VBB, and these wells and connections must be managed and planned for in addition to implementing the required circuitry.

• The staggered circuitry inherently causes asymmetry in the performance of the different wordline drivers. The goal should be to minimize these differences as well as model them in the verification of the final implementation.

As you can now imagine, the unrestricted dimension of a wordline driver can grow very quickly as we try to stagger a driver cell in the pitch of memory cells. Figure 5.27 shows a floorplan of a possible solution.