COMPUTER-AIDED DESIGN (CAD) TOOLS FOR LAYOUT

INTRODUCTION

Every year at the biggest conference for IC CAD known as the Design Automation Conference, VLSI designers from around the world are bombarded with names of new products and methodologies that can improve the efficiency of design.

Before the conference, magazine and e-mail advertising is frenzied, and during the conference, presentations and demonstrations are given all day long. In all of them the marketing and salespeople presenting the tools always feature new options and benefits such as extra capacity and quality, a variety of menu options, and the very “important” price/performance ratio in comparison to manual methods or tools from the competition. None of these presentations discuss the philosophy of the tool, what the designer of the tool had in mind, what new concepts the tool is addressing, or what kind of flow the tool is supporting.

We learn about buttons, ease of use features, values to enter into forms, but not the real reason why we should use the tool. In many cases, new tools that have good potential are not successful because they were not introduced with the right approach.

The vendors who market their tools to the right users are always more successful than others who don’t, even if those others have a better tool. During the past 15 years many companies tried to build tools to totally eliminate the work of a layout designer by offering a “push-button” solution. However, most of them have disappeared.

As an example, while working at Motorola we received a demo of a new tool for layout design. The application engineer who came to present the tool started the demo with the following statement: “This is a tool that will provide an engineer with everything he needs to avoid using the services of a layout designer!” I don’t think that I have to explain how successful the demo was and how a wrong marketing motto helped a very capable tool to fail.

Their timing was good, the tool was very capable at the time, and with some good customers and an installed base, it could have become the market leader. They were the first to see the advantage of integration between layout and circuit simulation databases. In this case the developers addressed the needs of one group of users by creating a disservice to the other. For obvious reasons, we will not give you the name of that tool in this book.

In this chapter we try to cover for each family of tools the concepts that we understand they are addressing and the methodologies required to use the tools. For a comprehensive list of vendors and tools, check out the Integrated System Design Magazine Web site, where there is always an updated vendor list.

A description of the basic types of tools used for layout today in CMOS VLSI designs is outlined next. Subsequent sections will expand on features and ideal usage of specific tools based on the flow and the context where they are or can be used.

The various classes of tools have been grouped into three areas, as shown in Figure 10.1.

Planning tools include the following:

• Floorplanners: A floorplanner is used to coordinate placement and routing engines to create a layout floorplan. Floorplanners are discussed exten- sively because they pose new concepts and challenges for layout design. When used properly, floorplanners can reduce time to market by provid-

ing a methodology for top-down design and layout that is correct by construction.

• Placers: A placer optimizes the placement of cells or devices using physical and logical constraints. Placers are generally designed to work with specific routers; therefore, it is very important to use a placer and router from the same vendor. This is because the two tools work together to meet the constraints and take advantage of features and information that are known to both tools.

To understand more about this topic, we will expand on the features and constraints of placers in the sections related to specific levels of design. Once understood, it should be clearer why it is better for a placer and router to work together. As a simple example, a channel router needs channels to route with, so the placer must provide these channels. If not, the world’s best placer may be useless.

In terms of types, there are three basic levels of placers, each having different features and requirements:

Inside cells—transistor and cell placement

Inside blocks—cells, blocks, or mixed cell and block placement Chip level—block-level placement within a floorplanning tool

• Routers: Routers were the first automation tools that were widely used. A router enhances the speed of layout interconnect. At first routers were capable of chip-level routing; they have evolved to handle cell-level routing today. A router is a must when the complexity of connections is beyond the capabilities and efficiency of a manual approach.

Layout generation tools include the following:

• Layout editor: A polygon pusher or layout editor is used to generate polygons and paths using a graphical user interface. Some of them are very sophisticated and may include place-and-route functionality.

• Symbolic editor: A symbolic layout editor has the same user interface as a polygon pusher. However, the layout is generated symbolically from a coded or mathematical algorithm that is programmed into the tool. The advantage of this approach is that the process design rules are used as parameters to the code; therefore, it is easy to generate layout for different processes.

• Device generators: Device generators are used to generate layout devices such as transistors, via arrays, or logic gates. They typically have an extensive graphical user interface and a highly developed macro language. In some cases the device generator is an enhancement to a layout editor or an independent tool. Without a placer or a router, device generators have very limited value for enhancing productivity.

• Compactors: A compactor automatically optimizes existing layout and is generally used as an enhancement to an advanced layout editor or symbolic layout tool. The compactor shrinks or enlarges the width and space between polygons with a goal of minimizing the layout to the limits of the process design rules.

• Silicon compilers: Silicon compilers are used to generate layout automatically by generating transistors, leaf cells and structures using the leaf cells based

on a standard architecture. In general, silicon compilers do not have a graphical user interface, as they are used to process a large number of structures. They are developed mostly by and for people with a lot of software experience.

Finally, the layout support tools include the following:

• Layout verification tools: Layout verification tools perform a suite of tests on completed layout. Design Rules Checkers (DRC), Layout versus Schematics (LVS), Electrical Rules Checkers (ERC), Layout Parasitic Extraction (LPE), and optical proximity tools are discussed.

• Plotters: Plotters are generally not a software tool, but in order to produce meaningful and readable hard copy of layout, software specifically designed to process layout is normally used.

• Converters: Layout converters are often called migration tools. Similar in concept to compactors, a converter is used to retarget or compact a previous design into a process with different design rules.

Finally, a discussion of data formats for layout databases will be presented.