A Complete Example: An RTL Cache

A Complete Example: An RTL Cache

In this section, a direct map cache module, developed in RTL SystemC, will be discussed. The header and implementation of this module are shown in Figure 89.38 and Figure 89.39, respectively.

As shown in Figure 89.38, the sample Cache module has a set of signals for connecting to a CPU (e.g., read, write, and ready) and a set of signals for connecting to a memory module (mem_read, mem_write, and mem_ready). The interface between this cache and CPU is byte-by-byte, while its interface with memory is block-by-block, using blk_address and blk_size ports.

The cache memory is modeled with an array of 128 logic vectors, as shown below. A logic vector in this array stores a 16-byte block of data from memory.

The module developed here is actually a cache controller that is a state machine with seven states (s0 to s6). This state machine consists of two methods named cache_op and state_change (as shown in the SC_CTOR part of Figure 89.38). The state_change method is sensitive to clk and reset signals. This method changes the present_state at the positive edge of clk.

The other method (cache_op) performs cache operations in each state. It is sensitive to the read, write, mem_ready, and present_state signals (Figure 89.38). As shown in Figure 89.39, it has a case-statement with all possible values of states. In each state, it performs specific tasks, asserts proper values for its memory and CPU side signals, and defines the value of next_state. This variable is used in the state_change

method. Predefined functions for logic vectors, like range and to_unit, are used in this method. The state machine, shown in Figure 89.39, is depicted in Figure 89.40.

As an example, consider state s2 in cache controller state machine (Figure 89.39 and Figure 89.40). The state of state machine changes to s2 if the CPU asserts the write signal. In this state, data and address values are read and the corresponding block of the given address is checked. If this block is in the cache memory (word variable), then the given data is written into the corresponding address of the block (cache hit happens). If a cache miss occurs, there are two situations that can happen.

One situation is that another block resides in place of the corresponding block of the given address (dirty bit is 1). In this case, the current block must be written back to the memory, the corresponding block of the given address must be read from the memory, and the given data must be written to the given address of the newly read block. These operations are performed by going from s2 to s6, s6 to s5, and s5 to s0, respectively.

Another situation is that the corresponding block of the given address is not occupied by any other block (dirty bit is 0). In this case, this block must be read from memory, and the given data must be written to the given address of the newly read block. These operations are done by going from state s2 to s5, and s5 to s0, respectively.