LAYOUT DESIGN:INTRODUCTION TO CMOS VLSI MANUFACTURING PROCESSES

INTRODUCTION TO CMOS VLSI MANUFACTURING PROCESSES

There are many kinds of design processes, but this text discusses only CMOS technologies. We will first discuss the manufacturing order of layers (Figure 3.1) without going into the details of how each step is physically realized.

We start with a bare silicon wafer. Between steps an isolation layer is grown to protect areas that are not to be patterned.

P and N bulk regions are defined by differentiating different areas of the wafer with “wells” or “tubs” of the appropriate type.

The polysilicon that forms the gate areas is added next.

Source and drain areas are defined by diffusing areas on either side of the gate polysilicon. Other active areas such as substrate contacts and guard rings are formed at the same time.

In order for interconnect layers to be connected to the polysilicon and/or active areas, contact holes are created in the isolation layer on top of the layer to be connected.

The interconnect layers are deposited and fill the contact holes created in the previous step.

The last layer is called the passivation layer with openings for wire bonding connections. The passivation layer is a glass layer that isolates the chip from the external world.

This diagram is a very simple explanation of the manufacturing process. Different process technologies have significantly different manufacturing steps.

DRAM memories for example have four layers of polysilicon to construct the memory cell capacitor. ASIC designs have only one polysilicon and more layers of metal, which are used to connect many, many logic gates. Using five to six layers of metal, microprocessors, and other complex ASIC designs can be produced (Figure 3.2).