SYMMETRY OF LAYOUT DESIGN TECHNIQUES TO ADDRESS ELECTRICAL CHARACTERISTICS.

SYMMETRY

Predictability in the behavior or performance of a design can be thought of in many ways. For example, in measuring the timing characteristics of a circuit, it is desired to meet an absolute performance target. Often it is desired that two layout designs be implemented identically so that the performance characteristics of the two circuits relative to each other match.

Following are examples when symmetry is routinely used:

• Differential amplifiers require operational matching between halves of the cell layout

• Datapath and memory array circuits require identical layout for each row and column

• In layout designs where parallel structures are used to build up a cell, such as a multiple-finger NAND gate, tweaking any series connectivity in the different parallel paths will remove asymmetries between the series elements

• Differential pair routing requires matching characteristics between signals

• Designing signal and clock paths to meet flip-flop setup and hold times is an exercise in matching signal paths to the clock path

The best way to ensure that two circuits behave identically is to use the same layout cell in both cases. Signal symmetry is achieved by designing two signals to have the same length, width, load, and coupling environment. These concepts are discussed in more detail. Note that in extreme cases all the techniques described in this section can be combined for very sensitive applications.

Symmetrical Layout

In many analog, RF, or sensitive digital designs, two halves of a particular design are electrically equivalent, and it is desired that each half perform identically. A differential amplifier is an example where the circuit’s function is to distinguish signal differences between two input signals.

A very simple technique to achieve almost perfectly symmetrical layout is to use one cell twice. The minor differences between the two cells should be implemented on top of the cell. Figure 7.19 illustrates this approach.

Advantages and disadvantages of this approach are as follows:

• Symmetry is guaranteed and easy to implement

• The benefits of cell-based layout come into play. Changes to both halves are done in one cell.

• The cell planning is a little more complicated because the symmetry point has to be understood and the layout implemented with this in mind.

• There may be some area or routing overhead because of the symmetry, but polygons along the line of symmetry are usually shared.

A practical tip: Use the “Edit in Place” mode built into almost all layout editors to develop the base cell. Edit in place one of the two base cells from the top level cell so that changes made will appear in the other half instantly.

Balanced Layout

We define a balanced layout as a design that has symmetrical performance as a result of intelligent connectivity within its structure as well as a symmetrical layout.

Often, implementing balanced circuitry has the following effects:

• Reduced power in a world where designers are dealing with the large power consumption of today’s chips and are trying to avoid needing fans to cool chips down to the optimum working temperature.

• Timing symmetry. This is especially important in analog and RF designs, where the timing of each switching device is critical.

• Definition of more detailed connectivity models to accurately capture the balanced nature of the design.

Analog design technique is the father of balanced layout, where a very old method called “balanced devices” is applied to IC design. The example shown in Figure 7.20 illustrates the concept for a two-input NAND gate, and the result is that the delays between both inputs to the output are the same.

The schematic shown on the right side of Figure 7.20 shows exactly how the schematic is defined for Example 3. Many LVS layout verification tools have algorithms to recognize NAND gates within the layout. The layout NAND shown in Example 3 is not often recognized as a NAND and creates discrepancies when compared to a regular schematic NAND. The reason is that the order of the series connections within the NAND is reversed. Functionally, they are equivalent and in fact balanced. In this case the schematic must be altered to reflect the correct connectivity in order for the LVS to pass.

Balancing circuits is not always as straightforward. Balancing series devices is more difficult when dealing with more than two transistors connected in series. Figure 7.21 shows an example of three series gates to illustrate this concept further.

In order to balance the series connections, each input is connected to a transistor in each of the three positions: close to out, center, and close to power. This is only possible if there are three parallel series chains; therefore, introducing balancing to a layout may incur significant overhead.

Physical Compensation

Physical compensation is the term we use to describe the concept of layout symmetry applied to signals. Signal symmetry is achieved by designing two signals to have the same length, width, load, and coupling environment.

Designing signal and clock paths to meet flip-flop setup and hold times is an exercise in matching signal paths to the clock path. In some cases where the timing margins are extremely small, physical compensation techniques are used.

Synchronous DRAMs (SDRAM) are an application where input setup and hold times are required to be very well defined. Circuit performance needs to be guaranteed under all voltage, temperature, and process conditions. Physical compensation is appropriate in this case.

As we have mentioned, signal symmetry can be achieved by mirroring many structural features of the signals among the group to be compensated. This should include numbers of vias; matching of routing layer(s) and the length of the sections in each layer; and shielding each signal equally.

A short list of steps to implement physical compensation among a group of signals might be as follows:

1. Route signals as you would any other signal, and reserve space for length compensation and shielding lines. Route all lines using a single width of line.

2. Determine the longest line among the group to be compensated and increase the length of all other signals to match. Serpentining signal lines is appropriate as long as adequate shielding is maintained.

3. If different routing layers are used, match the length of interconnect on each layer for each signal. It is not necessary to place the different layer routing in the same place along the line, but it is important to use the same number of vias within each signal.

Match the relative transistor loading or fanout for each line. This means that the ratio of the size of the transistor load relative to the driver should be the same for every line. Additional transistor loads should be added to the appropriate signal to match the fanout ratio.

4. Table 7.3 illustrates the concept of compensation load calculations.

5. Run layout extraction tools to verify the results and adjust the layout if necessary.

Figure 7.22 shows a simple routed group of signals before compensation is applied. Note the arrows. The small arrows indicate areas of overhead space allocated for the physical compensation that will be applied later. The long arrow at right shows the size of the bus.

Figure 7.23 shows the same layout after compensation. Note that the final height of the bus is greater than before, indicating that the plan was too aggressive (the small arrow indicates the difference).