LAYOUT DESIGN TECHNIQUES IN AN UNCERTAIN ENVIRONMENT:PLANNING FOR UNKNOWN CHANGES.

PLANNING FOR UNKNOWN CHANGES

During various phases of design, layout designers are challenged with design rule changes, circuit changes, bugs in the software tools, etc. The best medication is prevention, but we don’t always know what to expect. In a DRAM chip, if any of the major memory layers gets a minor design rule change, it may not be efficient to use the planned architecture, so the entire core layout and design should change. Such process changes have much less impact on the layout of ASIC designs, because their processes are much simpler and because most of the layout is done using place-and-route tools.

Planning for unknown changes might seem strange at first, but we can always estimate the amount of change of a particular design based on the novelty of the design and the experience of the circuit designers. In general, when planning at the chip level, most numbers are “wet finger” values. Even using the most advanced tools for floorplanning, there is no way to envision the final architecture, the final number of gates, or the total number of signals, for that matter. The best solution is to plan the chip with change in mind, and to forecast the type and amount of change based on personal experience.

As an example, if a design is estimated to have 50 percent of the circuitry that is completely new, we can start to plan on 50 to 60 percent of contingency in our work. With this in mind, spare logic, area, signals, etc., can be reserved to cope with design development and changes. Using this approach will give the final design a much better chance to end up a success.

Conversely, if contingency planning is not done, the size and schedule of the initial design will grow and grow to the point where the project will be at risk. We can tell you a secret: “everything is possible in layout” where only the imagination is the limit, but more and more, “time to market” is the real limitation. Preparing a plan that can accommodate changes at any stage with minimum schedule changes and almost no change in chip size is the dream of all project leaders today. Plan for change when starting any part of the design, because people make mistakes, and the dream can become reality.

Last-minute changes are handled using a formal procedure called an Engineering Change Order (ECO), described in the next section. Before we receive and have to act on one of these, there are many methodologies we can implement that will help us handle these emergencies. This section outlines a few of them.

Contact and Via Instances

The concept of a hierarchical design was described in detail in Chapter 3. There are many benefits of using hierarchy, and in the context of planning for change, the use of hierarchy is key to minimizing database management issues when reacting to large-scale changes.

This section is devoted to discussing the merits of contact and via cells specifically because there are many benefits to them. Place-and-route tools use them for connections, but the concept was developed before the advent of these tools.

The idea was to develop a library of cells for various types of contacts. This practice is effective when there are three to five types of contacts, but in the case of DRAM memories in particular, this concept really improves layout efficiency. DRAM memories have many poly layers, but also have multiple design rule sets, so there is a great range of contact and via cells. It is not uncommon to have a library of two to three dozen cells.

Historically, contact cells contained a single polygon: the contact layer alone. The idea that we are proposing (within MOSAID it is standard procedure) is to create the contact cells including all three related layers. For example, a contact between active and metal1 will be a cell that contains contact layer, active, and metal1 overlapping the contact. The layout conforms to the design rules completely so that the contact “cell” is DRC clean.

Some advantages of this approach include the following:

• Advanced rules such as the “metal end overlap” rule can be implemented globally without too much effort.

• The cells are DRC clean, so other designers will create layout that is correct by construction. The idea is that the contact cells are by definition correct, as with standard cell libraries for an ASIC designer.

• Defining naming conventions for each chip with multiple design rule sets will help layout designers to use the appropriate cell. Also, they do not have to memorize the different contact design rules—only those for the region they are working in.

• Cell names are portable from project to project. Memorizing numerical design rules is not.

• Contact cells are easy to connect to, since touching or overlapping the boundary of the cell is sufficient.

• The biggest advantage is when the time to tape-out is critical. In “bleeding edge technologies” such as memory designs, when people start the layout of a chip, the process is not yet fully defined. Many times in my experience, this solution saved the tape-out. In many cases we had to change the contact size, the overlap layers rules, or just the contact layer. Under normal conditions, all these changes will require some CAD soft- ware “processing,” but such actions have to be checked and debugged before they are applied to a full chip. Using contact cells, it takes about 5 minutes to complete a global process change, with guaranteed success in our experience.

Because we found this feature very efficient, we decided to use it everywhere. We are trying to convince all the vendors offering transistor-level automation to

embrace the contact cell as a feature in their tools. In Figure 9.5 we can observe some examples of contact cells, including all their overlapping layers.

Minimum Design Rules?

Another approach to accommodating change and preventing major impacts on the layout design is to avoid using minimum design rules or minimum area design methods all of the time. This is especially valuable if it is known that the design under development is new or has a high probability of change.

Consider the scenario of an analog design, where the designer may not know from the start the internal routing scheme of the block. In this case the final sizes within his or her design will vary based on the final results obtained from layout extraction.

How can a layout designer prevent moving contacts, devices, and cells to accommodate anticipated changes? In this section, we outline a solution.

We learned in previous chapters that one of the important steps in layout design is to try to use source/drain sharing actives as much as possible to reduce the size of the area. In case of “expected” changes, the layout should be built in such a way that it could accommodate limited size changes. Figure 9.6 illustrates a technique that accomplishes this.

One side of the empty channel is power connected, while the other is an output. This is the output of a transistor that is likely to change.

The technique that is used here is to space the active regions by the amount that accommodates a finger of gate poly. The spacing may not be minimum, but allows significant flexibility in changing the transistor size.

Spare Logic and Spare Lines

Even if the most advanced tools and experts are used, a chip will always have some dead space central enough to make the idea of spare logic gates and spare lines worthwhile. Unless the chip has a flat netlist and the design team is using an automated place-and-route tool, any design will end up with holes of unused area.

After expending the effort needed to implement last-minute changes and after feeling the pain of bug fixes and mask revisions to revise only a small portion of a design, many designers have accepted the idea of placing unused or spare gates and signals on the chip before tape-out.

A simple technique is to devise a block of logic that comprises a common group of logical functions and place the cell in any free area in the chip design. The quantity and types of gates that are used may vary from chip to chip based on a forecast of what may fail. The design of the block is heavily metal oriented so that connections and reconfiguration of the transistors are easily done using a minimum number of layers. The gates are disabled initially in such a way that they do not affect the normal operation of the chip.

Combined with spare lines that connect various regions of the chip and passing by the groups of spare logic, fixes to minor bugs become much easier. Additional lines are not a great impact on chip size when compared to missing a market window.

Figure 9.7 illustrates this concept of inserting spare logic into empty areas that have good access to spare lines. Spare lines are routed in every channel, and

in general up to 5 percent of the number of signals in the channel should be spare not including routing requirements for the chip finishing stage. During the prototyping stage, it is a good practice to have at least two spare lines per channel. The spare lines respect channel metal directions and are fully connected from one end of the chip to another. Using numerous local spare structures, global changes can be implemented without any chip size or schedule impact.