ADVANCED TECHNIQUES FOR BUILDING-BLOCK INTERCONNECT LAYOUT DESIGN:POWER GRID

POWER GRID

Power supply lines such as VDD and VSS are the most pervasive signals on the chip. Consider that they connect to virtually every gate and block; they each have many pins on the package; and they carry a lot of current and therefore must be sized appropriately.

The need to manage power issues very carefully in IC design has grown over time. More complex chips result in larger power grids. Voltage levels on chips have been decreasing over time from 5 V to 3.3 V, but the operating frequencies have increased. The net effect is that the power consumption of ICs today has increased. There are also many more low-power applications with cell phones, PDAs, and laptop computers. These applications really benefit from power management techniques. CAD automation for power management has been developing as well and this adds another area of expertise to study and master.

The logistics of implementing a power grid requires planning and should be one of the first things to consider when floorplanning a design. Power lines need to be planned to surround as well as flow through blocks. Adding power lines after a design has been implemented is extremely painful because typically a large and pervasive structure is needed for multiple power lines, and this is difficult to insert once a design is complete.

Remember that the goal is to provide adequate power supply connections that will meet electromigration requirements and resistance characteristics for all circuitry on the chip. Wide, short lines will meet both of these goals; however, large supply lines will inevitably consume more area. It is this trade-off that we need to manage.

In conclusion, planning and estimating the requirements for power lines should be an integral part of the layout design process.

Power Estimation

The first step is to calculate how much power each block will consume and there- fore estimate the minimum size of the supply lines that will meet the block’s requirements.

There are many ways to attack this problem, but one essential point is to do it as early as possible to avoid major rework late in the project schedule. The problem now becomes a lack of detailed information, because the design- ers do not know exactly how many gates will be in their block and exactly at which speeds they will be operating. Please realize that this will be an iterative process.

One very good approach is to base our estimations on a previous design, taking from it the architecture, power estimation numbers, and power routing. Extrapolating the data for the new chip we have to review:

• Differences in process constants. For example, determine if the metals are inherently more resistive or capacitive, or if they have significantly different electromigration rules.

• Check process parameters for all vias and contacts.

• Number of metals available, especially for the power routing. You may be able to take advantage of more or suffer with less.

• Speed of each block. Different blocks may operate at different clock frequencies and this will affect power.

• Size (in terms of number of gates) of each individual block.

• Possibility of multiple power branches, based on the noise introduced by high-speed blocks. It may be necessary to isolate noisy blocks by having sep- arate power supply lines.

• Number and position of power pads to determine overall routability and resistance paths from the pads to the different blocks.

Power Supply Routing

Assuming we have been able to gather enough information from the estimation stage, it is time to plan and implement the power supply tracks to a chip floorplan.

There are many approaches to address this problem but we will describe only two basic approaches:

1. The “root” approach: In this case the power line starts as wide as possible, and as the power is connected to various blocks, the power supply lines become thinner, similar to the roots of a tree.

• The width of the supply lines is based on the electromigration factor and is tapered in proportion to the quantity of current being consumed along each branch of the root.

• This approach is used when the resistance of the supply lines is not an issue for any block along the chain.

• Historically, most power routers routed power using this approach.

2. The “resistance” approach: In this case the power network may look much as it does in the root approach, but the tapering is based on a calculated resistance from the supplying pad to the specific block in the chain. The amount of resistance that is tolerable is determined by an acceptable voltage drop through the power supply line as calculated by Ohm’s law.

• The width of the supply lines is based on the resistivity of the metal used for routing the supply.

• Number of vias is very carefully calculated to help reduce the total resistance or to ensure that via resistance is not a limiting factor.

• The choice of metal should be based on lower resistivity values

• Routed metal should be implemented such that changing layers are M1 » M2 » M1 instead of M1 » M2 » M3 » M2 » M1.

• In some specialized and fast chips, there are metal layers dedicated to power supply level only in order to reduce power supply resistance and ensure a consistent power supply level to all parts of the die.

Figure 6.1 shows the differences between these two basic styles. Most chips will use a combination of these two methodologies.

Strapping and Tapering

When we talk about power lines and chip layout techniques, we need to apply the concept of strapping. The idea was presented in Chapter 5 when we discussed the wordline strap cell.

The idea of a “power grid” consists of supplies routed and strapped together to form a mesh of signals. Section 6.1.2 outlined the approach of routing a power supply signal, and this section deals with the design of completing the power grid with the appropriate amount of straps and tapers. As in power routing, the amount of strapping can be determined based on electromigration or resistance, but also depends on the overall style and complexity of the design.

For example, in a standard cell block design there are specific tools that analyze power consumption and power supply resistance within a row of cells and automatically strap the power between rows to generate a solid power grid.

Certain gate array architectures have a built-in power grid with vertical strapping of power at predefined intervals.

Table 6.1 shows two examples of equivalent power grids under different conditions. Various factors can be used to determine these numbers; examples of

those that should be used are power consumption, clock rate, average fanout, duty cycle, electromigration, and resistance.

To more fully understand Table 6.1, note the following:

• There is a direct relationship between the maximum strap spacing and the M1 width inside the cells. The relationship is defined by the resistance of the power supply line and its connection to the power supply grid. A connection to the power grid is assumed to be robust in this case.

• These numbers show an example for a 0.25 mm process and demonstrate the relationships between the different supply line widths.

Figure 6.2 graphically shows the difference in the two cases outlined in Table 6.1.

As we can see from Figure 6.2, if greater routing porosity over the cells is required, this can be achieved by paying the penalty of cell height in order to increase the required M1 power supply lines.