HDL-Based Tools and Environments:CAD Tool Vendors and Summary of HDL-Based Tools and Environments.

CAD Tool Vendors

Cadence

Cadence Design Systems, Inc. was established in 1988 through the mergence of two electronic design automation (EDA) pioneers—ECAD, Inc. and SDA Systems. Since then, Cadence provides a series of CAD tools used in hardware design in different abstraction levels from layout to system level [3]. Cadence design technologies include:

• System-level design

• Functional verification

• Emulation and acceleration

• Synthesis/place and route

• Analog, RF, and mixed-signal design

• Custom IC layout

• Physical verification and analysis

• IC packaging

• PCB design

Cadence provides a series of simulators called NC-Verilog, NC-VHDL, and NC-SC used for simulating Verilog, VHDL, and SystemC designs. These simulators are employed in a verification platform, called Incisive, used for design verification in any abstraction level from gate level to system level. The BuildGates is the synthesis tool of Cadence that generates a Verilog net-list. Then Encounter does all the other tasks including floor-planning, placement, clock tree generation, routing, timing analysis, power analysis, and signal integrity. Encounter Test is used for ATPG and DFT design and analysis.

Magma

Magma design automation provides EDA software that enables chip designers to handle multimillion-gate designs. Magma’s complete RTL-to-GDSII design flow includes design planning, prototyping, synthesis, place and route, and signal and power integrity chip design capabilities in an integrated environment [4]. Magma’s software also includes products for advanced physical synthesis and architecture development tools for programmable logic devices (PLDs) and capacitance extraction.

Magma’s Blast Create provides a predictable path from RTL to placed gates. It is an integrated environment for general logic and high-performance data-path synthesis, DFT analysis and insertion, physical synthesis, power optimization, and static timing analysis. Blast DFT provides test quality and yield management within Magma’s design flow. It supports several DFT strategies such as full-scan ATPG, memory and logic BIST, and TAM and Boundary Scan. Blast Power provides a solution for power optimization and management.

Mentor Graphics

Mentor Graphics provides an event-driven simulator called Modelsim that supports assertions. This makes it a useful assertion-based verification tool. Modelsim can take Verilog, VHDL, System Verilog, or SystemC inputs [5].

Leonardo Spectrum of Mentor is an RTL synthesis tool that converts its Verilog, VHDL, and System Verilog input into net-lists for both ASIC and PLD targets [5]. The designer can adjust the synthesis process to optimize area, delay, or both.

DFT advisor is a testability analysis tool and test synthesis tool used to insert full scan into the design. It also provides several methods for partial scan selection [5]. LBISTArchitect is a BIST insertion program that analyzes the testability of the design and synthesizes test structures into the design and finds the design’s fault coverage.

The ATPG tool for full-scan design is called FastScan. It uses an innovative compression method to generate compact test vectors. It supports extensive fault models, including stuck-at, IDDQ, transition, and path delay. FlexTest is an ATPG tool for nonscan or partial scan designs. It supports fault simulation for functional vectors and also supports stuck-at, IDDQ, transition, and path delay fault models.

Synopsys

Synopsys provides a simulator called VCS that takes standard HDLs including Verilog, VHDL, System Verilog, and SystemC as input. It supports System Verilog assertions that make it suitable to be used as a verification tool [6].

Synopsys Behavioral Compiler is a high-level synthesis tool that allows users to synthesize behavioral HDL input descriptions. DFT Compiler enables designers to quickly and easily implement high-quality test early in the design flow. DFT Compiler supports RT-level and gate-level scan design rule checking, constraint-optimized test synthesis, and fault coverage verification.

Synopsys also provides a power analysis tool. PrimePower is a dynamic full-chip power analysis tool for complex ASICs.

Summary

In this chapter, a typical VLSI design flow was presented and based on it several required CAD tools including simulation tool, synthesis tool, verification tool, and test tool were described. In each case the different types and different implementations were described. Finally, we introduced the four major CAD tool vendors and some of their products.