ADVANCED TECHNIQUES FOR BUILDING-BLOCK INTERCONNECT LAYOUT DESIGN:INTERCONNECT ROUTING.

INTERCONNECT ROUTING

After we have solved power routing and clock tree issues, we can attack the general routing requirements. Special signal requirements will be discussed in Chapter 7. Let’s review the proper order for routing signals:

1. Power supplies

2. Clock signals

3. Buses

4. Special signals—to be discussed in Chapter 7

5. General routing—the topic of this section

Routing Plan

The goal of a routing plan is to determine the overall complexity of the routing to be implemented, identify areas on the die specifically for routing only (these areas are known as routing channels), and address potential bottlenecks or prob- lems in achieving a completely routed design. In addition, the impact of the routing on the final chip area can be estimated. For example, dedicated routing channels can be estimated and included in a chip floorplan.

Here is a list of steps to achieve a viable routing plan.

1. Signal Estimate. Without a final schematic or netlist, it is impossible to identify exactly the number of signals that will be required to connect all of the blocks. No matter how good the plan is, it is still a forecast of the future and will be wrong. Please understand, however, that any plan, no matter how sketchy, is infinitely better than no plan at all.

Without a finished circuit design, we can still estimate the total number of signals. This total is a good guideline for planning purposes, and if we group or relate the signals to different blocks, we can start to get a feel for areas of congestion.

A signal estimate can be based on the following:

• Asking experienced layout designers who have previously planned similar style of chips to give an estimate based on their experience. Their knowledge is invaluable in areas of congestion, blocks that have a low or high signal count by their nature, or areas that were significant problems in the past.

• A size estimate and preliminary pin list of each of the major blocks in the design.

• Signal source and destination—from where to where they have to be routed.

A simple schematic diagram using blocks drawn only for the purpose of estimation (not 100 percent correct or complete) done by the architect of the chip can be very helpful. This diagram would show a preliminary location for all of the major blocks and reflect the size estimate and aspect ratio for each of them. Figure 6.4 shows an example floorplan.

• List of major busses and special signals.

• Pad list and their positions around the die.

Using all of this information, we can estimate: the location of major channels and the size of the routing channels in terms of the number of signals per channel.

If routing is allowed over the blocks, then we need to take this into consideration when defining the size and location of the channels. In this case it is useful to do a hierarchical signal plan and consider the routability of each of the blocks.

2. Establish Routing Direction. The routing direction for each of the layers needs to be decided on a channel-by-channel basis. The floorplan is a good way to visualize the optimal choice of routing direction.

Different scenarios for layers used in each channel should also be considered.

These issues will be explored further in the next section.

3. Contingency Plan. Finally, features and overhead to handle major changes to the design should be built into the plan. For example, spare lines and extra space should be built into the plan. The amount of overhead to deal with major changes could be determined base on the following factors:

• The novelty of the design. Newer designs will have greater uncertainty in the estimates of block sizes, signal count, and pad positions.

• The stability of the process. The routing layer design rules may change and become larger or smaller, and this would significantly affect the routing plan.

• A guideline of 10 percent is a good rule of thumb for designs of average complexity and novelty.

4. Monitor and Update. As the circuit design matures and more details on the blocks and the overall chip are available, the routing plan should be updated.

It is the process of addressing all of the foregoing concerns that results in a practical routing plan. Issues in regard to die size, congestion, and routability will

be exposed and dealt with at an early stage. Once the circuit design is finalized, the routing plan will make the final implementation of the design significantly more straightforward and less error prone.

Channel Ordering and Routing Direction

Now that we have established routing channels in the routing plan, we can start to examine each of the individual channels in more detail. Each channel has been identified as containing a certain number of signals.

What are our concerns? Essentially, the goal of planning the channels is to prioritize and order the signals in the bus to optimize the following criteria:

• Circuit performance requirements: Critical path signals, signal resistance, and capacitance

• Channel area: Channels can be optimized to avoid jogging and unnecessary layer changes, especially as signals switch from one channel to another In fact, if channel area is optimized, in most cases the circuit performance is optimized at the same time.

A simple procedure for manually implementing and optimizing a channel is as follows:

1. Add an unnamed path for each signal in the channel.

2. If there are critical signals that are known to be important, label them first and determine their place in the channel.

3. Label and place signals that traverse the full length of the channel.

4. Label and place signals that start or end in the channel.

5. If it is known that a signal simply goes around a row of logic to an adjacent channel, then consider adding feed-throughs to accomplish this. This is discussed in more detail later in Section 6.3.3.

6. Use the remaining space to label and place local signals. Local signals start and end in the same channel.

7. Note that the placement of cells may increase the availability of local inter- connect lines as shown in Figure 6.5. Refer to Figure 6.6 for an example of placement performance reflected in channel size.

8. Leave spare placeholders for lines in the channel to anticipate new and unknown requirements.

9. Reorder the signals if necessary to optimize or minimize the number of vias or layer changes as the signals round a corner from one channel to the next. Figure 6.7 shows an ideal channel order that minimizes the overhead of signals changing channels. Not all the automatic routers have this feature!

10. Make a plot of the completed design to identify more changes that will optimize the design.

As we have mentioned, the routing layers within a channel should be deter- mined separately for each channel. It is not necessary to define the routing layer

direction for the entire chip and to enforce a set direction religiously. As we will see, channel area can be optimized by a judicious choice of routing layer for each channel, depending on the routing requirements of the signals.

Standard routing directions for each layer should be maintained for power supplies, special signals, and wide buses. These classes of signals are global and thus benefit from standardized layer assignments.

Key factors that determine the optimal routing layer within a channel are as follows:

• Intelligent ordering of signals for those that turn a corner as demonstrated in Figure 6.7.

• The pin layer for the cells will determine the layer that connects the signals in the channel to the cells. Note that the reverse is also important to consider, in that if a specific channel routing layer results in a smaller or more efficient layout, then the cells should be designed to take advantage of this fact.

• In general, signals to be routed parallel to a row of cells use the same layer that is routed in the same direction within the cells.

• Local signals that simply cross a channel offer a variety of choices of routing layer. Figure 6.8 illustrates three examples of this situation. We can observe that the signals in Block B are in the same order but at different locations compared to the ones in Block C. This is a typical case of only one layer in all directions. Such an approach here will provide the best size and symmetry for the bus in question.

Note the following from Figure 6.8:

• A single-layer route is only possible if the ordering of signals crossing the channel is maintained.

• Channels 2 and 3 do not suffer from the need for vias, as shown in channel 1.

• Routing is blocked in both routing directions in channel 1. Vertical routing is free and clear in both channels 2 and 3.

• Channel 3 is implemented using only one layer, but in fact the channel is the same size as channel 1 as shown by the ghost routings. This implementation of the 45-degree signals does not result in area savings. Also, 45-degree layout is more time-consuming to generate.

• Channel 2 is the best layout of the three: the layout is symmetrical, there are no vertical routing blockages, and the channel is smaller than the others.

Using Feed-throughs

As the name implies, a feed-through is a routing track that simply passes through a structure without making any electrical connection within that structure. This concept was introduced in Chapter 5 as a method of passing a signal through a row of standard cells.

Let us now consider using feed-throughs in the case where we have blocks and channels. The floorplan is crucial and is an invaluable representation of the design to allow us to analyze and optimize signal routing. This optimization can occur even before we have completed the internal layout of blocks, and it is at this time that the routing analysis is most valuable. Routing requirements can be anticipated and built into the block design. The advantages of floorplanning cannot be underestimated!

Consider the scenario shown in Figure 6.9, where there are a few signals from block A to block B that are being routed around block C. There are many

ways to resolve this problem, so let’s assume that blocks A and B are complete and cannot be changed. Block C is still under development and can be altered.

The right side of Figure 6.9 shows the effect of adding feed-throughs to block C.

• Block C is longer in this example to accommodate the extra signals. This implies that there were not enough routing resources in this direction and on the desired layer to accommodate these signals.

• The signals from A to B are now much shorter.

• The distance between block A and block B is less because the channels to block C have been significantly reduced.

• Block C becomes higher because we added signal on the height dimension— or it may happen that there were enough routing resources to cope with additional signals.

• The ports in blocks A, B, and C must be aligned.

• The verification of block C will need to include the results for the additional signals. Labeling of these signals is a good idea to ensure that these will be treated as feed-throughs and will not inadvertently be used in another manner.

In an environment where many changes and additions are anticipated, there are layout design approaches that will be friendlier to feed-through after the

layout is complete. These techniques can also be used if lower level blocks are being implemented without floorplan information.

Anticipate additional routing or incorporate spare routing resources into the block design. Note the following:

• This approach may affect the block porosity and introduce overhead to the cell area. At this point it is not known if the routing space will be used!

• Identify the unused routing resources appropriately so that they will not be forgotten.

• Identify areas that are unavailable for routing to avoid mistakes.

• Ensure that the block performance is not affected by the added parasitic capacitance of the extra polygons. Similarly, if the routing resources are not used, the block performance should be verified as functioning properly.

• The simplest solution to most of these issues is to include the routing resource as part of the cell and manage the overhead of verifying the block with the extra lines. The characteristics of the block are most predictable in this case.

Another solution is to design the block in sections that can be readily split apart to accommodate extra signals. Figure 6.10 shows how this might be accomplished.

Note that by using this approach, we can add circuitry as well as routing resources.

Remember that the last two approaches are rarely required if floorplanning is used! Also, these techniques are valid for layout of small and large cells as well as blocks.