LAYOUT DESIGN:PREPARING TO START

PREPARING TO START

The most important stage in any kind of layout design is the planning stage. Quality in layout means that the end results, the final layout, meets the customer’s (i.e., the design engineer’s) requirements. To achieve quality results, a layout designer has to prepare a list of input requirements, taking into consideration all the specifications and a list of output requirements in order to ensure that output layout requirements are met.

Developing a Layout Floorplan

Now that we understand how to build single transistors and the concepts behind design rules and manufacturing process, we can start to plan our layout with some sound fundamental knowledge.

We need to remember the concepts presented in Chapter 2. The schematic or netlist that we have been given to lay out has undocumented or implied electrical and performance characteristics that need to be implemented for an optimal design. Ideally, a list of documented requirements is supplied with the circuit design. Ask for it! We have one suggestion that can be of tremendous benefit at this point in the design process but is not indicated in the procedure. Depending on your familiar- ity with the type of layout you are about to start, it is always a great idea to do a bit of research to familiarize yourself with the circuit involved. It is extremely rare that you are about to attempt something that has never been done before!

Ask to see previous designs of the same type or in the same process. Ask who the expert is on this type of circuit. Review the concepts in this book if it has been a while since you last did a layout of this type. An appropriate amount of time to look for information to reuse and help you in your work usually pays off. Get a second opinion on your work (by reusing someone else’s) before you even start!

Of course, the flip side of this approach is that it also pays to make your work and knowledge available to everyone else as well.

To ensure that nothing is missed, a prelayout checklist from the notes from your research is a great way to plan out a strategy for laying out a design. Figure 3.22 shows an example of a general procedure for creating a layout plan based on the circuit design requirements.

The first step, 1.1, is related to the planning of the layout of the power sup- plies and/or global signals. The power supply connectivity is typically called the power grid. Power supply resistance from the interface to all parts of the design must be considered. In this case special attention must be applied to the width of the supply lines and the grid or mesh of power lines through the design. Again the interface to other designs is important, especially in the case of a cell design where it may be desired to array it or have seamless abutment requirements to other cells. Let’s not forget that tub and substrate contacts are typically connected from the power supplies, so a strategy to lay out these contacts must also be considered.

Step 1.2 is to list all of the input and output signals. Each signal is assigned a position on the interface of the design to the neighboring designs. The interface is defined as the boundary of the design. In some cases certain signals will have a specific or nondefault signal width assigned to them. Special considerations for signals may include clock signals, signal buses with multiple bits that need to be matched between them, critical path signals, and shielded signals.

In Step 1.3 we have to deal with special design requirements such as layout symmetry, specific requirements for latch-up protection, or noise immunity. More examples of special design requirements might be that the design must be pitch matched (i.e., limited in size in one direction), must have a very specific critical path signal, or might be a nonstandard part of the design.

Step 1.4 is very important to help finalize the size of the design and estimate the feasibility of meeting all of the design requirements within the area and schedule constraints. Using any previous knowledge about older designs of the same complexity and the process design rules, a layout designer can approximate the size of each component and the complete design. The number of different components to be implemented can be identified and the overall hierarchy or partitioning of the design can be completed. Areas for internal routing and signal connections should be allocated. The routing layer in each interconnect area should be identified. Extra signals or space should be reserved since we have only an educated estimate as to the size of the final design.

At this point we should have a preliminary floorplan and implementation strategy. The floorplan should comprise a definition of the interface or boundary with all of the signal ports assigned to their proper locations. Signals with special requirements are identified, and the area impact of these special signals is included in the total area estimate. If it is a hierarchical design, subcomponents are also known with their respective interfaces defined. Spare space and spare signal lines are included in this plan.

Step 1.5 is a sanity and cross-check to confirm that all requirements have been met and none missed. There are requirements related specifically to layout guidelines and styles for the process, but also circuit design requirements as well. The floorplan is a communication tool between the layout and circuit designer, as the circuit designer most likely had defined some specific requirements for his or her design and had assumed some kind of layout floorplan in modeling the design

for its environment. It is very important to involve the circuit designer in the audit process.

The layout audit also relates to the next level of integration for the piece that you designed. The “brick” that you have now floorplanned has to interface perfectly to all of its neighbors and their interfaces; otherwise, when put together it won’t work exactly as planned. As an example, the top-level chip design has to fit within the context of the chip package, so a review of any floorplan is very important. The person responsible for integrating your design should audit this floorplan as well to review the requirements related to size of the design, the layout architecture or approach, and your designs interface, among other things.

It is not uncommon for audits of really complicated floorplans to require two people: one to check the engineering requirements and another to check the layout needs. The auditor(s) should be a person who is not directly involved in the design, but who has the expertise to evaluate and appreciate the floorplan quality, and to make constructive comments. To help the auditor perform a proper audit, ideally a checklist is used for each type of layout design. Refer to the addendum checklists for some examples.

Stick Diagrams

Stick diagrams are a simple way of floor planning a circuit in preparation for layout. In many cases it is very useful for circuit design engineers to sketch for themselves a simple layout drawing without respecting any design rules, in order to imagine more realistically how the layout can be done and if it can be done at all. Circuit design involves many assumptions about how the final layout may look, so an easy and fast stick diagram can enhance the chance of a successful design. Stick diagrams can be done with various levels of detail that we will not go into here. An example is shown in Figure 3.23.

Step 1 shows a preliminary placement of all of the devices. In this case the VDD and VSS power line architecture has been predefined, as has the orientation and location of PMOS and NMOS transistors.

Step 2 shows the procedure for identifying which actives are connected to the same potential, and also the effect of flipping devices in order to take advantage of “sharing” these nodes.

Step 3 shows the final result of the active sharing. This is, in fact, the final layout with the interconnect optimized. The cell is narrower than in the previous steps. We can use this last version of the stick diagram as a floorplan for the audit mentioned in Section 3.7.1.

Hierarchical Design

As mentioned in Section 3.7.1, the circuit design analysis and resulting floorplan may indicate that it makes sense to have a hierarchical design. A hierarchical design is one that has a reference or uses another component as part of its construction. These subcomponents in turn may reference other components. This is similar to the concept of a subroutine in a computer program.

Building a design using subcomponents makes a lot of sense for the following reasons:

• Computer resource management: Data that is already occupying disk and memory space is easily referenced as opposed to making a separate copy of the data.

• Component reuse: Designers can reuse components that are already fully completed—they have been designed, verified, and audited, preferably by experts in those areas.

• Concurrent engineering: Partitioning a design into different subcomponents allows many different tasks to be completed in parallel.

In terms of layout design we refer to these reusable subcomponents as leaf cells. The term leaf cells comes from the fact that a hierarchical design resembles a tree with a trunk, more primary branches, many more smaller branches, and finally, many, many, many leaves.

A few comments about leaf cells:

• They are repeatable layout designs that can be reused in many different regions of the chip.

• They can be made out of one polygon—i.e., contact cells; can be made out of three polygons—i.e., contact cells made with the surrounding layers (metal1, metal2, via12); or can be a complete circuit—i.e., inverter, NAND, flip-flop.

• They may have different versions of the layout for one version of the schematic because an inverter of equivalent size in the I/O region will have a different cell environment or interface than one in the memory region of the chip.

• Any group of polygons using a standard interface makes sense to be made as a leaf cell. For example, a library of logic gates all generally have a stan- dard power supply layout interface, and so it makes sense for each of the gates to be a cell. If a design of multiple logic gates is to be implemented, it is not recommended that the design be done at the transistor level. Making logic gate cells first is preferred.

• If global changes are required to a design, it is much easier if cells are used.

Imagine updating a design with 100 inverters. Consider the case of one design with an inverter cell instantiated 100 times versus another “flat” design with 200 transistors connected as 100 inverters. A change is required to all 100 inverters. In the case of the inverter cell design, the inverter cell is updated. Depending on the change required in the 200-transistor case it is likely that it would be more efficient to start the design over from scratch using cells than to try to update all 200 transistors.

• Conversely, using our 100-inverter example again, we must be very careful if only 1 of the 100 cells requires updating. We cannot change the inverter cell without affecting the other 99. In this case a second inverter cell is required that reflects the required updates and we replace the one outdated inverter with the new one.

• Every cell in a design needs a unique identifier even if it is a second instantiation of an already designed cell. In our example of the design with 100 instantiations of a cell called INV, we need to identify each one uniquely (i.e., INV001, INV002) and the identification of the cell should match the name that is used in the circuit design if there is an electrical correspondence. This instance name is needed to differentiate each of the physically identical INV cells. This is very useful in our example of changing 1 out of the 100 invert- ers, as we can use the instance name to identify the outdated inverter.

• Cells can be flipped and rotated much more easily than groups of polygons.

• If a symmetrical layout is required, one cell representing one-half of the design is all that is needed, and this techniques guarantees that the resulting layout is perfectly symmetrical!

• Cells can be scaled, although this is risky because of issues with polygon coordinates becoming off grid.

• Computer screen redraw resources is minimized using cells as all polygons within a cell need not be shown. It is often necessary to show only the key interface polygons and leave the details of the cell hidden.

• Cells can be “arrayed” to save more computer resources. An array can be thought of as the definition of a matrix of cells. For example let’s consider the case of implementing a 10 ¥ 10 matrix of memory cells. We are given a single memory cell as the leaf cell. One option is to instantiate the memory cell 100 times (this results in 100 X,Y coordinates, or 200 numbers that not only must be stored—we have to generate them as well!). A better option is to define an array that requires an X,Y origin, an X,Y offset, and the number of rows and columns (six numbers!).

• The use of cell arrays also reduces computer screen redraw time. For example, certain software packages have options to display only the border cells of an array. Another option would be to display only the corner cells.

• Hierarchical layout verification tools can take advantage of the repeated use of a smaller number of cells versus many individual ones. In our example of a design with 100 instantiations of a single inverter cell, conceptually a layout verification tool needs only to verify the inverter cell once and then check how each of these cells interfaces to each other. This approach is much faster than verifying the case of 200 transistors connected as inverters.

Figure 3.24 shows examples of cells instantiated in a design with instance names and different orientations. The stylized letter F attached to the cell origin shows the layout designer the orientation of the cell.

From Figure 3.24, please note the following:

• Base cell name = AGBC in all cases

• PDC is the name of the top hierarchical cell/block

• Instance names are different every time a cell AGBC is instantiated in the design, e.g., comp001, comp002, comp003

• The first example shows all the cells are oriented at 0 degrees relative to the origin of the PDC block

• The second example shows the instance comp002 is flipped versus the other cells—observe the two arrows that define the mirror axis

• The third example shows an array implementation