HDL-Based Tools and Environments:Verification Tools

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Verification Tools

As mentioned before, there are two ways to inspect the correctness of the design steps: simulation and verification. Simulation methods were described in Section 96.1 and this section is dedicated to the verification methods. Verification methods are classified into two categories:

• Assertion-based verification: In design validation using simulation, the simulation results should be inspected manually. In an assertion-based verification, assertion monitors are used to check the simulation results continuously. The designer provides several properties to show the correct behavior of a circuit and develops the assertion monitors to check that these properties are not violated. When a design property is violated, the assertion triggers and alerts the designer. A set of common assertion monitors are provided in the open verification library (OVL).

• Formal verification: After completing a design, the designer provides a set of properties to show the correct behavior of the design. The process of property checking is called formal verification. A formal verification tool tries to match a property with the specification of a design and if it is unsuccessful, it finds the input conditions that make the property fail.

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