LAYOUT DESIGN FLOWS:MEMORIES

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MEMORIES

A very wide variety of memories are on the market today. Memories are a commodity part, as they are produced in high volumes for general-purpose consumption. A memory is conceptually simple: its job is to store data for retrieval at any time.

Examples of memory ICs are ROMs, dynamic and static RAMs, EPROMs and EEPROMs, SDRAMs, FRAMs, and SLDRAMs. The full list is quite long. Here is a short glossary of the different types:

• ROM (read-only memory): The contents of memory are fixed and can only be read.

• SRAM (static random access memory): Operates very quickly and remembers the data as long as power is supplied to the chip.

• DRAM (dynamic random access memory): Similar to an SRAM, but denser and needs to be refreshed periodically or else the data is lost. The data is dynamic.

• PROM (programmable read only memory): Generally programmed once and used as a write-once, read-many-times device. Can be electrically pro- grammed and/or erased as well.

• HDRAMTM (high-density random access memory): An embedded memory macrocell implemented in an ASIC process technology. The advantage of this is that a special manufacturing process is not needed. MOSAID Technologies Inc. has patented many of the techniques used for HDRAM.

In terms of design flow, memories are all very area intensive. Key metrics to memory effectiveness are the density and efficiency of the memory.

The relationship with the process specialists is very tight because memory processes are in general one generation ahead of others. They have to be ahead in terms of minimum manufacturing gate size, i.e., 0.25, 0.18, or 0.11 mm, because the memory chip depends heavily on process characteristics. If in a microprocessor we can get today 10 million transistors, in a DRAM memory the number has easily passed 256 Mbit for production.

Memories are implemented using full-custom techniques, and this fact shows the emphasis on area as the key issue. Every micron counts in memory design! Consider that current DRAM memories contain 256 Mbits per chip. Any reduction in the area of the memory cell reduces the chip’s area by the same amount—multiplied by a factor of 256,000,000!

An obvious feature of a memory is that it is a very repeated structure with many cells that are pitch-limited in one direction. Therefore, in terms of design flow, the memories have a very interesting bottom-up and top-down design methodology. The chip and memory architectures are defined first, and then all layout starts from the memory cell and builds outward. The chip size is deter- mined primarily by the memory cell size and the associated layout around the memory cell, so careful full-custom layout techniques are used.

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