System Level Design Languages:TLM Design Process and TLM Implemented in SystemC

By -
TLM Design Process

A design process begins with a high-level specification of the system being designed. The design step, which must be taken after this description becomes available, is to generate a transaction level model. For this purpose, we have to define our top-level modules and their means of communication. Module granularity and specification may be refined in the next stages of the design process. Accordingly, the functionality of communication channels and their interfaces will also be refined. Defining these interfaces and channels can take advantage of a standard TLM library. If any of the communication processes have complex functionalities, application-specific channels and interfaces must be implemented based on the TLM library primitive channels and interfaces. Figure 86.76 shows the process of developing a transaction level model. The next section describes the structure of TLM library developed in SystemC by OSCI (TLM 1.0).

A simple example in SystemC follows this discussion.

TLM Implemented in SystemC

As stated in the previous section, TLM is a modeling concept that can be implemented in any system level language (e.g., C++, System Verilog, and Java). The first implemented version of a TLM library for system level design was in SystemC.

At the present time, most universities and companies that work on TLM and system level design use this language. One reason for choosing SystemC is the wide use of C++ language by software developers. C++ is a powerful programming language with several constructs for both a system and a software design. For example, C++ class definition and inheritance capabilities make it useful for defining interfaces and channels. To make SystemC more useful for hardware description, basic channels and interfaces are described in this language. Other useful interfaces and channels can be built on these predefined interfaces and channels in SystemC.

The TLM library, discussed in this section, has been implemented in SystemC 2.1 by the OSCI organization.

In this version, the main focus is on implementing a generic set of TLM interfaces and channels. The object passing semantic is based on the sc_fifo message passing of SystemC. In this library raw C/C++ pointers are discouraged to avoid memory problems caused by pointers. In this library, most of the implemented classes are template classes. This feature provides generality for the classes.

Communication APIs in this library can be unidirectional or bidirectional. They can also be in blocking or nonblocking modes. When performing a blocking data transfer, the caller must wait until the data transfer is completed. In the nonblocking mode, the transfer function will return the status of the data transfer immediately (whether it is done or not). In SystemC, the blocking mode data transfer can only be done in SC_THREAD and SC_CTHREAD processes. Nonblocking data transfers can also be done in SC_METHOD processes (see Section 86.3).

The implementation of this library includes several subdirectories. Each directory contains one or more C++ header files for TLM functions and their necessary implementations. These directories are discussed below.

System Level Design Languages-0253

• tlm_adapters: In this part, two classes named tlm_transport_to_master and tlm_slave_to_transport

are defined. These classes are useful for transporting data to/from a master or a slave.

• tlm_event_finder: Classes implemented in this part are used in blocking and nonblocking ports. These classes provide static sensitivity for these ports. The defined classes in this part include tlm_blocking_get_port, tlm_nonblokcing_peek_port, tlm_nonblocking_put_port, and tlm_event_finder_t class for handling events.

• tlm_fifo: Operations and necessary classes for a FIFO channel in TLM are implemented in this part. One of the main classes defined in this part is tlm_fifo. This class, a part of which is shown in Figure 86.77, includes basic operations of a FIFO such as get, put, peek, size, and kind. These operations are implemented in both blocking and nonblocking modes.

• tlm_interfaces: Basic interfaces are implemented in this part. There are two main classes named tlm_master_if and tlm_slave_if for sending and receiving data. These classes are shown in Figure 86.78. Also there are these classes for FIFO interfaces: tlm_fifo_debug_if, tlm_fifo_put_if, tlm_fifo_if, and tlm_fifo_config_size_if.

System Level Design Languages-0254

Comments

Post a Comment

Popular posts from this blog

Square wave oscillators and Op-amp square wave oscillator.

By -
Image
Square wave oscillators If Fourier analysis is performed on a square wave it is found that the waveform is composed of many harmonics of the fundamental frequency. This rich harmonic content makes the square wave particularly useful as a quick test of amplifier performance. Examples of possible results are shown. The simplest way to produce a square wave is to make a sine wave oscillator in one of the ways described earlier, then feed the output to some form of squaring circuit such as a Schmitt trigger. This is the method adopted in most commercial sine/square wave generators. There are, however, several circuits for square wave oscillators and a description of the most common follows. Multivibrator Technically the multivibrator is a relaxation oscillator, working on the charging of a capacitor through a resistor. If a negative edge is applied to the circuit in (a), transistor TR 1 turns off the for time taken for the base voltage to return to 0 V. If the voltage step is
Read more

Adders:Carry Look-Ahead Adder.

By -
Image
Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f
Read more