Multidimensional Logarithmic Number System:Binary to One-Digit 2DLNS

Binary to One-Digit 2DLNS

Since the table method for converting single-digit 2DLNS-to-binary (shown in Figure 84.2, simplified from section 3) is quite fast and can be implemented efficiently in hardware, it seems only logical to reverse this process: i.e., to convert a binary 2’s complement representation into a single-digit 2DLNS. This is a three-step process where the first step is not easily reversible, while the last two steps of shifting and sign correction can easily be performed on either 2’s complement or FP formats.

Table 84.3 shows the contents of the LUT for D = 3 and R = 3. The number of table rows is 2R (8, for this example). The precision of the mantissa is C = 10, where C is the number of bits of the fractional part.

Sign Determination

For 2’s complement conversion, the sign of the binary input, x, is generally the high-order bit. If x is in an FP format (e.g., IEEE-754), the sign is determined from the FP sign bit (unless x = 0, a special FP

case). In the event where s = 0, the 2DLNS exponents will also be set to 0 to minimize the chance of arithmetic overflow when performing simple 2DLNS operations (multiplication and division). Once the sign is extracted, |x| is found.

Normalization

From the MDLNS to binary conversion, a shifter is used to set the output properly based on the sum of the input binary exponent and the LUT pseudo-FP exponent. For the reverse case we are trying to find the value of the binary exponent. Originally shift = a + e(b), but can be rearranged to a = shift - e(b) where shift is the number of bits |x| has to be shifted to normalize it (i.e., set it between 1 and 2). e(b) will be provided from the reverse of the LUT operation. For 2’s complement this basically requires a priority encoder, whereas, for the case of FP, |x| is already represented in a normalized form. The number of shifts can be determined from the exponent portion of the FP notation. However, this method is only valid for normalized FP notations. Denormalized FP notations (i.e., values <2-126 for 32-bit FP and 2-1022 for 64-bit FP, including zero) will require additional hardware as in the 2’s complement case.

Reverse LUT

The input to the single-digit 2DLNS-to-binary LUT is the second base exponent, b, and the outputs are the mantissa and the exponent. To reverse the process, the input to the LUT is now the mantissa, m(b). Since the mantissa is not influenced by the exponent e(b), it can remain an output. Table 84.4 shows a preliminary binary-to-single-digit 2DLNS LUT for D = 3 and R = 3. The complexity of the unused portions of the LUT (the nonshaded area) is O(2C); however, since the table contains undefined entries for all possible input values except for the 2R values that are exactly representable (shown as ¯ and referred to as ranges) the complexity of the required storage area is only O(2R). The shaded table entries, downward, are formed by mantissas doubling and exponents decrementing by 1. Shaded table entries, upward, have mantissas halving and exponents incrementing by 1. These complexity expressions exclude any calculations based on the output bit widths since they are considered a constant.

To reduce the LUT complexity to O(2R) (i.e., 2R ranges) the undefined entries must be removed and the input range restricted to that of the normalized mantissa (the nonshaded area in the table). The latter is achieved by the normalizer, whereas the removal of the undefined entries can be achieved by rounding any input in an undefined range to the nearest representable value (i.e., using a mid-point function between the defined addresses). The complete LUT for D = 3, R = 3, and C = 10, is shown in Table 84.5. Note that an extra range is required owing to the possibility of rounding up numbers near 2.0. Thus, the number of ranges is 2R + 1, but the complexity is maintained at O(2R).

The following example demonstrates the use of Table 84.5 in performing a 2’s complement binary- to-single-digit 2DLNS.conversion.

Unfortunately, to build a conventional LUT (similar to Table 84.5), all possible values of the mantissa must be accommodated in the address decoder, which increases the complexity to O(2C ). Clearly, the conventional LUT address decoder is not appropriate for this memory architecture.

Range-Addressable LUT (RALUT)

A standard LUT architecture is shown in Figure 84.3, where an address decoder is used to match the address to a unique stored value. The RALUT architecture of Figure 84.4 shows the new address decoder system that matches a stored value to a range of addresses. The decoder compares the input address, I, to a range of two neighboring monotone addresses (e.g., Addr(1) and Addr(2)). Only one of these comparisons will match the input and activate a word-enable line which drives the data patterns, Data, to the output, O, of the RALUT.

We can remove half of the comparators in the range decoder by noting that

The optimized uniform architecture is shown in Figure 84.5. Further gate-level optimizations can be made; however, to keep this discussion brief, they will not be shown here.

The contents of the RALUT for D = 3, R = 3, and C = 10 are shown in Table 84.6. The input column contains the values for which (I ³ Addr(n)) match (beginning range of each row in Table 84.5) and the output columns contain the associated outputs. The RALUT architecture is optimal since it requires only 2R + 1 rows.

Binary-to-Single-Digit 2DLNS Architecture

The complete binary-to-single-digit 2DLNS architecture using the RALUT is shown in Figure 84.6. This structure can be implemented in a single (low latency) or multiprocess (pipelined, higher latency, lower power) circuit depending on the system constraints.