LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS:STEP COVERAGE RULES

STEP COVERAGE RULES

For each type of design, ASIC or DRAM, for example, the processes are very different, as we have already explained. Based on the purpose of the chip, market prices, design requirements, etc., companies are developing special processes. The variety of design rules for each of these processes continues to evolve.

Layout designers are not involved in processing, but they have to take measures to prevent possible problems during the chemical and physical processing of the wafer. One problem that can be addressed with proper layout design techniques is the step coverage effect.

A “step” in this context refers to the rising or falling slope of a layer as it passes between chip areas where a different number of layers exist underneath. For clarification, see a DRAM memory cell area versus the neighbors and the concept of friendly cells (Figure 5.23).

A process using a technique called planarization alleviates this problem, as the surface of the wafer is leveled with isolation material between layers. In this way, the steps are removed.

Why is this “step” a problem? If we analyze Figure 8.8, we can see that when metal1 is routed along a poly line, the angle defined by the height of the poly generates an irregularity in the metal cross-sectional shape. The layer is no longer the desired rectangle, but an odd shape that does not have the same characteristics as a straight line of metal running over a flat surface. In an extreme case, the metal line may physically break!

For example, if a via is placed on top of the irregular metal, the connection is likely to fail or be very unreliable. Figure 8.8 also shows the same situation for a planarized wafer, and the result is much better.

A design rule and layout requirement related to planarization is a rule defining specific density goals of a given layer over a specific area. For example, a rule might state that within areas of 100 ¥ 100 mm2 regions, metal polygons must cover at least 75 percent of the area. The idea here is to implement enough polygons to ensure proper planarization for the layers above.

In order to meet this requirement, the layout may need to contain dummy or extra polygons to ensure that the process achieves layer consistency over the entire region. In some cases, designers can set up the layout verification tool to automatically find the density problems and fill the area with the dummy layer. These layers may electrically float, but in general they are connected to power supplies and add to their decoupling capacitance at the same time.