LAYOUT DESIGN FLOWS:ASSPs

ASSPs

An application-specific standard product (ASSP) is a standard product that has been designed to implement a specific function, as opposed to a general-purpose product such as a DRAM. In general, at first big companies had a monopoly over VLSI design, and most of them developed products that would sell in large quan- tities. These are standard products, not ASSPs.

Startup companies looking to leverage a certain area of expertise or define niche applications typically produce ASSPs. Today we have chips in almost every part of our lives: answering machines, car diagnostic computers, Global Posi- tioning Systems (GPS), cellular phones, coffeemakers, and power supplies for various appliances. Each of these applications requires specific chips, and to be profitable in a competitive environment, the startup companies had to develop new methodologies that required new tools.

Designers of different ASSPs use slightly different design flows, because the ASSPs can be classified into different types as outlined in the following sections.

DSPs

Digital signal processing, or DSP, is carried out by digital circuits designed to address a broad class of problems in signal reception and analysis that have traditionally been solved using analog components. DSP is rapidly replacing analog signal processing functions where requirements for stability over time and temperature variations are critical. DSP is used to enhance, analyze, filter, modulate, or otherwise manipulate standard real-world functions, such as images, sounds, radar pulses, and other signals, by analyzing and transforming waveforms (e.g., transmitting data over phone lines via a modem).

Based on the complexity of the design or the cost of development, DSP designs can be implemented in an ASIC flow or in a flow that is similar to the microprocessor flow, in that it is primarily a full-custom flow.

ASICs

Application-specific integrated circuits (ASICs) are semiconductor circuits specifically designed to suit a customer’s particular requirement, as opposed to DRAMs or microcontrollers, which are general-purpose parts.

The challenge of an ASIC flow is that typically the design is new and specialized, and there is no previous history on which to base architectural decisions. In this case there is significant emphasis on defining and verifying the architecture of the design.

Another characteristic of ASICs is that the designs are heavily biased toward logic structures. The design entry of this type of circuitry is tedious in a full- custom environment and not practical for designs exceeding 5,000 transistors. HDL methodologies therefore are standard for these designs where transistors are completely hidden from the designer.

In terms of layout, the picture is very similar. The layout designer is no longer involved in transistor-level design and architecture, but in block-level using advanced place-and-route tools. He may not actually see the full layout view of the library because for place-and-route purposes the obstruction shades are enough to generate complex blocks or chips. We will develop the library concept further in the next chapter.

Now, let’s see how an ASIC flow works and what the various stages are to complete a design (Figure 4.2).

1. Architectural/behavioral design: See the definition of chip architecture in Section 4.2.

2. RTL design: Designers are developing and reviewing system-level and functional Register Transfer Level HDL code and implementing the desired functionality. Verilog and VHDL are the standard languages used for this function.

3. Logic design: Digital or functional simulations are performed as part of validating a behavioral model of the intended design. The simulation verifies that the chip architecture is feasible and will perform the desired operation.

4. Logic/timing optimization: This step is the most famous one and has revolutionized IC design from the days of full-custom schematic-based designs. The HDL code implemented in previous steps is useless without the ability to synthesize the code.

In this stage, synthesis tools require two inputs: the design functionality in terms of RTL code, and a standard cell library with synthesis views and timing information. For each function coded within the HDL, the synthesis tool will chose the most appropriate library cell or combination of library cells to perform the job. The end result of synthesis is a netlist that contains standard cells and their connectivity.

5. Place-and-route: Place-and-route tools (P&R) are automated tools that require the following:

• Standard cell library physical information, i.e., cell sizes, points of connectivity, timing, routing obstructions

• A synthesized netlist that details the instances and connectivity relation- ships including constraints and critical paths in the design

• All the process requirements for connectivity layers, including design rules of the routing layers, resistance and capacitance, power consumption, and electromigration rules for each layer

Using this information, the layout is implemented automatically and optimized for minimum area and ideal timing.

6. Timing extraction: This is a step to extract and calculate the timing of inter- connect signals after the cells are placed and routed. Delay information is produced that is fed back to the circuit simulator for reverification of the design after layout. The result of extraction is a file in a format such as Standard Delay Format (SDF). This file will be used to go back and annotate the netlist with the real values from the physical design.

7. Signal analysis: Using this new netlist, the designer can now resimulate the design and find if the functionality and the timing specifications are met. In general, there are many cycles of P&R, extraction, resimulation, and synthesis until the specifications are met.

8. Tape-out to manufacturing: When the circuit specifications and layout design rules are met, the layout data goes to manufacturing.

This is the basic ASIC flow that has evolved over the past 15 years. As the complexity of designs grew, the tools and methodologies improved. Improvements to the basic layout flow include the following:

• Increasing tool capacity: One competition in the P&R marketplace was about who can place and route more gates in one run. When the size of the chips grew to more than 250,000 placed objects, it became inefficient to do the job flat, so the market moved to hierarchical design.

• Introduction of floorplanning tools to the ASIC flow: Hierarchical layout is accomplished using floor planning tools that were previously used by the full-custom chip designers to coordinate hierarchical requirements between blocks.

In order to select the cells used by the synthesis tools, we must make many assumptions related to the interconnect delays. The initial methodology was to use statistical models of interconnect loading before a place-and-route job.

When the timing delay was 100 ns, it was possible to make an error of ±10 ns because of the variation in the placement and routing tools and the expertise of the designer. When the processes got to 0.25 mm and the timing of critical signals dipped below 10 ns, nobody could afford a 10-ns mistake. Therefore, the solution was to bring some physical information into the ASIC flow sooner.

How can we bring layout data into the floorplan before the chip has real cells and real interconnect data? By running a global placement algorithm and a global router, we can extract from layout for top-level routing loading information for these signals. The data is not 100 percent accurate, but it is much closer to reality than the assumptions made before.

Without floorplanning and global routing it took five to ten iterations to get to a final layout. Using floor planning and physical information earlier reduces the process to two or three iterations per design. It is not a single-pass flow, but it is converging more quickly to the desired result.

As will be discussed in detail in Chapter 10, there are many links between tools. Especially in the case of P&R, it is recommended that the links between the floorplanner, placer, and router be very close. Tight integration of all of these tools is essential.

ASM

Application-specific memory (ASM) is a chip based on the ASIC flow, but containing a large memory block. Almost every chip today contains memory parts. They can be static RAM, dynamic RAM, ROM, etc., but in general they are no more than 512 kbits in size. An ASM is a chip that requires a lot of memory, from 1 Mbit up to 64 Mbits. Examples are video RAM (VRAM), synchronous graphic RAM (SGRAM), and in some cases more complicated designs.

The design of a memory block as described fully in the next section is done in a full-custom style. If memory expertise is part of the overall design process, then the chip could be implemented in a full-custom flow as well, or an embedded memory block (IP) could be the answer. Large ASMs would really be classified as a system-on-a-chip flow as described in Section 4.5.