ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN:PAD CELLS

PAD CELLS

Every chip has an interface to the external world of the printed circuit board. The way an integrated circuit does this is through the pins of its package. These pins are connected inside the chip package to metal conductors that are collectively called a lead frame. The final connection to the chip is from the lead frame through gold bond wires to large metal areas that are called pads.

Pad cells are the layout cells that have the large metal areas or bond pads within them. It is natural and more reliable to make these layout structures separate cells to ensure consistency in characteristics for all pads. Pad cells usually incorporate several structures and are designed to provide the following:

• Reliable connection area for wire bonding

• ESD protection structure

• Interface to internal circuitry

• Optionally, the logic directly related to the function of the pad such as input or output buffers

Relatively speaking, bonding pads are very big, around 85 ¥ 85 mm, because the pad is a target for a mechanical machine that is physically soldering a gold strand of wire. The pad metal is the top layer of metal and typically has a very large via connecting the top layer of metal to the underlying layers.

Figure 5.15 shows the pad structure and cross-section to show the combination of the metals and passivation or overglass layer. Note that the passivation layer is a negative layer. By necessity, the pad is not covered by the protective passivation layer (a glass material that protects the die) and thus is an area that is vulnerable to dirt and other foreign objects. Also note that the two metal layers are connected through a large via. For a greater variety of via connections, please refer to subsequent chapters.

We can observe that the no-polygon zone refers to a distance that is measured all the way around the pad generating invisible arcs. This feature can be used for passing 45-degree lines in between the pads.

In most ASIC designs, the pads are placed in a ring surrounding the core logic of the chip so the pad cells are designed using special geographical rules for layout. This is generally known as a pad frame. As there are three main types of pad cells—power, input, and output—the pad frame is also known as the I/O region. Examples are shown in Figures 5.16 and 5.17.

Figure 5.16 shows staggered pad cells. This arrangement accommodates more pads, since the pads can be placed closer together. In this case, the manufacturer requires a different and more specialized bonding machine. The increase in bonding complexity and cost is offset by the ability to accommodate more pads and by having a smaller and more efficient die. Since the bond pads have to be a specific physical size, in some cases the size of the design may be determined by

the number of pads when the ratio of pad cells relative to the amount of logic is exceedingly high. It is desirable to avoid this situation.

Note that only the metal of the pad is in two rows. The power supply rings and transistors related to the I/O circuitry are still in one row. This is for consistency in circuit performance and ease of layout design and integration.

Let us now consider specific guidelines for the layout of pad cells. Remember that the primary requirement of the pad cell is to enable a reliable wire bond connection to the die.

• Pad size: Big enough to accept a wire bond. This limit is purely a function of the bonding machine; therefore, it is defined as part of the layout design rules.

• Pad spacing: Not only does the pad have to be a specific size, but pads need to be spaced far enough apart to avoid shorting two bonding wires together. This rule may be specified as pad center to pad center or from the edges of

the passivation opening. Again, the design rules will specify this amount, as it is derived from the limitations of the bonding machine. This is easily accomplished by building the pad cells to abut to one another and still obey this rule. This rule effectively defines the width of the pad cell. A smaller value may be specified for double bond pads where a short is not fatal because the underlying pads are connected together.

• Pad to other structure spacing: In order to avoid shorting a wire bond to internal circuitry, a spacing rule is typically defined in the design rules. This rule may be a manhattan value or sometimes is specified as a region defined by a radius from the pad.

• Pad to scribe spacing: In order to avoid damaging the passivation or pad structure during dicing, the pad needs to be placed away from the edge of the chip.

• No-pad zones: Some areas may not be easily bondable, such as chip corners.

• 45-degree connection to pad: As the pad cell is exposed to potentially higher currents from the external world, guidelines to avoid sharp corners and possibilities for concentration of charge are recommended. A simple example is to connect to bonding pads using 45-degree polygons.

• Pad cell origin: A trick to more easily extract pad locations for the bonding machine is to set the origin of the pad cells to the center of the large metal area defined as the bonding target. Simply by parsing the layout database for the pad cells and determining the origin of the cell, a list of bond pad locations can be generated.

Figure 5.17 shows examples of some of these rules. They are defined by the manufacturing facility, but in general, the numbers are sometimes negotiable. Design rules usually have a significant amount of tolerance built into the values. A competitive advantage may be achieved by tweaking these values, therefore using creative solutions and working with the process group to address them is usually fruitful.

Because the pad frame or I/O region is the interface to the outside world, there are special requirements to obey. Electrostatic discharge (ESD) and the issues surrounding large devices dictate most of the rules for this region.

What is ESD? Electrostatic discharge is the discharge of a large amount of charge into a chip. This charge can be fatal to a chip because it may physically damage transistors that are hit with the charge, much like a structure that is hit by lightning.

The magnitude of ESD can vary widely, but the duration of a pulse is usually very short. An ESD event can result in junction failure, oxide breakdown, unwanted charge injection, and fusing or opening of internal wiring.

The most common source of ESD is from the human body, when a person incorrectly handles an IC. The resulting voltage can be in excess of 20,000 V. Electrostatic damage to electronic devices can occur at any point from manufacture to field service. Damage results from handling devices in uncontrolled, low- humidity, or poorly grounded surroundings.

ESD protection structures are always built into the conduction paths from a bonding pad to internal circuitry and are part of the pad cells. These structures act as lightning rods and are intended to redirect unwanted charge away from sensitive internal circuitry.

How is this done, or what rules must be followed when implementing pad structures to maximize our ESD protection? Different techniques are used for input and output structures; these will be discussed in the following sections.

Output Buffers

The most complicated structure in the I/O region is the output buffer design. Here we will encounter many rules that address ESD issues.

Output buffers are large drivers that send a signal off-chip. The widths of these devices are in the range of 400 to 1,000 mm. The size will depend on the frequency, power, voltage levels, current drive and functionality, etc., of the buffer itself. These large transistors must be laid out with great attention to detail, because the area that they will require is highly sensitive and they can directly affect chip size.

It is not logistically feasible to show all of the features of output buffer design, but we will try to explain the most common problems and solutions.

Referring to Figure 5.18, we can explain a few of the output-buffer-specific rules and guidelines:

(a) Every layer, whether metal, poly, or active, is shaped as 45-degree polygons until the signal path changes layer through a contact or via. The reason is that by avoiding corners we can avoid power surges and charge concentration around 90-degree turns.

(b) The distance between the contacts and the gate on the pad side is much bigger than in the case of normal transistors. The reason is that in this way we increase the resistance through active from the contact to gate poly and reduce the voltage drop across the gate. This is done to increase the ESD protection characteristics of the transistor. In some cases, an additional implant layer is used for these regions to increase the resistance of the active layer for the same reason.

(c) The distance between the contacts and the gates on the power side could be minimal or as great as in (b), depending on the process requirements. Remember that power pins are also susceptible to ESD strikes; therefore, it may make sense to design the same ESD protection structure on the power side, too.

(d) As we can see from Figure 5.19, the current flows between source and drain in various symmetrical electric field arcs. In the case of contacts in the middle of the transistor, the field lines are equal and symmetrical.

When the contacts are placed at the end of the source/drain, the field lines converge near the edge of the active. In this region the resistance across the gate will be smaller. In case of an ESD strike, the current path will take the path of least resistance and will tend to concentrate in these areas near the edge. “Punch- through” to the substrate from the source and drain is more likely to occur here.

To avoid the concentration of the current at the edge of the transistor, we can increase the resistance of this region by enlarging the gate length. The amount we increase the gate length should be targeted so that Ra1 + Rg1 + Ra11 = Ra2 + Rg2 + Ra21, and the current from an ESD strike is evenly distributed along the width of the transistor.

In reality the phenomenon is much more complicated, but for layout purposes, we hope that this example of equivalent resistance is good enough.

Figure 5.19 shows two options for gate overlap termination, seen in the top or bottom of the picture. The bottom example shows the case where a poly connection to another layer is desired.

(e) Part of rule (d) includes other process-related rules specific to the edge of the active layer. Each company that manufactures chips has a few specialists in ESD, so we advise you to talk to them about any requirements they may have before completing your design.

(f) The width of the pad output connection is based on many considerations: electromigration, resistance of the metal, impedance and inductance of the package connection, and equal load between the output transistor fingers, among other things. There is a lot of approximation and “art” in choosing the right widths for the pad connection. In general, the process group typically has many “proven or recommended” values for everything in the I/O area.

(g) The width of the power connection depends in general on the power consumption of the output transistors and the issues in minimizing the power supply resistance to these transistors. In our example, all connections are shown in metal1. In today’s four- to six-metal-layer processes, power to output buffers typically runs in metal3 or metal4.

A chip with 32 or 64 data buffers switching at the same time will have large chip power requirements. Note that in general output buffers are sup- plied with special or isolated power lines that are not connected to any other transistors and are connected directly to independent power pads. The different power supplies may be interconnected either in the lead frame or outside the package, but at the chip level, the output buffers are connected to what is called VDDQ and VSSQ.

(h) Gate length is another important thing to remember to address. Because of the high voltage over this gate in general, the length is greater than normal. Again, process people can help us here. They test various gate lengths at various voltages and can recommend the proper gate length based on their experiments and the performance, power, and ESD requirements of the chip under design.

One last thing to note in conclusion. When working with special layout cells such as the output buffer, it is advisable to build a checklist for that region and have the cell audited in great detail.

Input Buffers

Input buffers accept signals from outside of the chip. In the specific case of an I/O cell, many of the ESD protection structures and techniques are built into the output transistors.

Nevertheless, input protection structures are required to protect the fragile transistors that buffer the external signal for internal use. These devices are designed and tested by the process people, so if a manufacturer is providing one to you in a specific process, the device is silicon-proven already.

In many cases the input buffer design may start before the process is well established so designing an input ESD protection device can be a tricky proposition. Figure 5.20 shows an example approach.

This solution is simply an adjustable resistor. Note that the resistor is made of an active polygon with 45-degree corners [recall rule (a) in the output buffer section]. Again, the active polygons are typically surrounded by a special ESD implant layer that has the effect of increasing the quality of the resistor.

The resistor is divided into three equal regions so that the resistance can easily be adjusted at a later date. The adjustment is used in the prototype stage only, and a fixed setting is chosen for the production design. During prototype evaluation, the resistance can be adjusted using a focused ion beam (FIB) machine that either adds or cuts the metal tracks. This has the added benefit of allowing damaged parts of the resistor to be bypassed.

There are many considerations for the design of this resistor:

• Choose the width and length of the resistor based on ESD requirements and performance characteristics.

• We highly recommend using more than one contact to connect a signal path that has the possibility of carrying high currents.

• The width of the metal line should not be minimum and must meet some kind of electromigration guideline.

• The dashed line between the metal contacts represents the main area of effective resistance. It not only demonstrates the area available that is effectively resistive, but it should be a drawn layer that can be used to create devices for LVS. LVSing these devices ensures that inadvertent changes to the cell are not made.