LAYOUT DESIGN TECHNIQUES IN AN UNCERTAIN ENVIRONMENT:GUIDELINES FOR PROPER LAYOUT

By -

GUIDELINES FOR PROPER LAYOUT

We described in previous chapters most of the basic layout concepts and methodologies, and now it is the time to summarize them in a consolidated list. The list is built based on the basic flow of top-down planning and bottom-up execution in design.

Chip Floorplan

• Learn the architecture of the chip from the designer, who has a vision of the possible blocks, power requirements, groups of signals, and new areas that were never designed in the company before.

• It may be possible to extrapolate from previous projects the size of some blocks and the number of signals related to them. We need this information to assess contingency for the chip and for each individual block.

If new types of blocks are to be developed, new flow and new tools may have to be brought in. If so, the project may need additional CAD support to introduce the new technologies. Place-and-route, compactors, new verification tools, libraries from another vendor, and IP blocks are only a few example of new technologies that may have to be included in the plan.

• Assess and compare process rules related to other known processes. The list includes the following:

Vertical connectivity diagram—especially in case of multiple poly types Resistance and capacitance of gate, metal conductors, vias, and contacts Electromigration values for each conductor layer

• Evaluate the routing layers and determine the routing grid for each layer.

Determine whether it makes sense to unify the routing grids to a single value for each direction for simplicity.

Layout Design Techniques in an Uncertain Environment-0151

• Calculate block size based on finger size (Figure 9.8) and add contingency based on the novelty of the design and the experience of the designer.

• Check package and define pad locations, especially for power and busses of addresses and/or data.

• Define power style and grid—power line widths based on electromigration or RC, and where the chip needs special power lines connections in order to achieve the allowed IR drop and resistance. In some advanced processes, power lines have their own routing layers.

• Evaluate the total number of signals; build channels including contingency and plan for spare lines and spare logic.

• Find repeated structures and try to reuse any possible piece to increase efficiency and reduce change impacts.

• Plan layout hierarchy and design to match each other as much as possible (same level and names). Even though the verification tools are fast today, debugging time is based on the user’s ability to understand the errors and fix them in a timely manner.

• Update the floorplan regularly by replacing the empty boxes with finished blocks and rerouting the interblock connectivity. This way, when all the blocks are done, the chip is complete.

Blocks

Block-level layout guidelines are as follows:

• Import from the chip level, the block size and port positions and try to stick to them.

• Define feed-through signals so the overall chip congestion inside interblock channels will be reduced.

• Define power needs and grid inside each block.

• Define critical path design and group the related cells to minimize routing.

• Plan for changes by having spare logic and lines.

• Try to improve efficiency by using automated tools. When the number of components is 100 or more, even a good layout designer will find it hard to respect all the design constraints for this many instances and still be fast. Even if the tool is providing 80 percent of the job, it is much faster and less prone to error if the designer uses assisted routing rather than hand connectivity.

Cells

For cell-level design, we offer the following overall guidelines:

• Define cell architecture—i.e., standard, full custom, datapath, etc.—and boundary rules based on the block plan.

• Define power style and widths.

• Define special requirements—i.e., symmetry, neighbors, critical path.

• Define transistor style based on speed, power consumption, and routing requirements (porosity).

• Verify the cell DRC together with neighbors. This eliminates all possibility of finding errors at a higher level of hierarchy.

Comments

Post a Comment

Popular posts from this blog

Square wave oscillators and Op-amp square wave oscillator.

By -
Image
Square wave oscillators If Fourier analysis is performed on a square wave it is found that the waveform is composed of many harmonics of the fundamental frequency. This rich harmonic content makes the square wave particularly useful as a quick test of amplifier performance. Examples of possible results are shown. The simplest way to produce a square wave is to make a sine wave oscillator in one of the ways described earlier, then feed the output to some form of squaring circuit such as a Schmitt trigger. This is the method adopted in most commercial sine/square wave generators. There are, however, several circuits for square wave oscillators and a description of the most common follows. Multivibrator Technically the multivibrator is a relaxation oscillator, working on the charging of a capacitor through a resistor. If a negative edge is applied to the circuit in (a), transistor TR 1 turns off the for time taken for the base voltage to return to 0 V. If the voltage step is
Read more

Adders:Carry Look-Ahead Adder.

By -
Image
Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f
Read more