LAYOUT DESIGN TECHNIQUES IN AN UNCERTAIN ENVIRONMENT:LAYOUT OF CIRCUITS DESIGNED FOR CHANGE.

LAYOUT OF CIRCUITS DESIGNED FOR CHANGE

Although changes to circuit designs are impossible to forecast, there are many cases where we can predict that some circuits will require tweaking. In this case structures to adjust the functionality or timing of a circuit are included in the schematic from the start. There are preferred layout techniques that are used to implement these circuit designs.

Metal Option Programmability

Metal option programmability is a methodology that is similar to the idea behind gate array design, but applied in very specific applications. The idea is to have a design that has a common set of base circuitry and layout and is “programmed” by different configurations of metal masks.

In the context of the layout of circuits designed for change, metal option programmability is the application of this concept to individual circuits. Gate arrays have the concept of a master slice where the entire die is programmable. Metal options refer to a specific design such as a delay circuit, control logic, or memory configuration that can be modified or customized in a much smaller way.

The applications of metal options are virtually endless and perhaps limited only by the designer’s imagination. However, examples where metal options are used and are very valuable include the following:

• Reconfiguration of the functionality of a design. In this case, different metal options would produce different end products from a design with a common set of base layers. The following are examples of features that can be reconfigured:

Operational features such as low power modes and test modes I/O interface standard: TTL, LVTTL, SSTL I/O data width: ¥1, ¥4, ¥8, ¥16, ¥9, ¥18 Power supply voltage: 1.8 V, 2.5 V, 3.3 V, 5 V

• Analog circuit fine-tuning such as resistor values or devices sizes. The example of an ESD circuit adjustment was discussed in Chapter 6.

• Evaluating new or unproven circuitry against an established design. For example, two circuit designs may be implemented on a chip and a metal option might be used to switch between them to compare one with the other. This is most useful for tricky analog circuits such as PLLs, input buffers, and oscillators.

• Circuit adjustment by switching in or out devices, cells, or logic gates.

Let’s examine in detail an example that is very common. Delay chains are one of the cases where metal options are beneficial, since they are used to solve many different and sensitive circuit design issues.

Figure 9.1 shows different versions of one schematic delay chain that is configurable between 0 and 3 delay stages.

The schematics show CLOSED or OPEN switches that correspond to short and open circuits. The dashed line denotes the delay path in each case.

How are these options implemented and used in the design flow?

1. A circuit designer provides a drawn schematic with the options correctly drawn.

2. Two additional layers are defined, corresponding to the OPEN and CLOSED switches. These layers must be associated with a mask layer in which the options will be implemented.

For example, it is typical to implement options in top-layer metal for a two-layer metal process; thus, the options would be associated with metal2.

Using separate layers and devices allows the layout verification tools to verify connectivity and ensure that the options follow established guidelines. These guidelines should reflect requirements for DRC and product test where these option areas can be used once again.

The drawing and DRC checking of the options must be implemented care- fully. CLOSED layers can at any time change to OPEN, so the layout design and checking should accommodate this flexibility.

Polygons drawn in these layers are considered devices similar to resistors and must be connected as shown in the schematic. An example layout is shown in Figure 9.2.

A design with metal options is a case where the layout can begin before the final configuration of options has been finalized. Once the layout has been completed, it is an extremely simple matter to change options from one to another, since the area and topology of the cell is not affected by a change in option layer.

1. When generating the final GDSII for tape-out or mask-making, the CLOSED layer is merged with the associated mask layer (in this case metal2) and the OPEN layer is discarded.

2. During prototype testing, the product test engineer can revise a silicon version of the circuit. One option is to use a focused ion beam (FIB) machine to alter the circuit once more. CLOSED option points can be opened or OPEN

option points can be closed using this machine. Another option is to use a laser to cut CLOSED options.

The guidelines for option layers mentioned earlier need to include limitations imposed by the method that is intended to be used on silicon prototypes.

3. Once the final configuration of the options has been established using silicon-proven results, the schematic and layout database need to be updated to reflect the final settings.

Remember that FIB modifications to a particular die apply only to the FIBed chips. Therefore, if changes to the masks are required, this must be done by updating the layout database and regenerating the required masks.

Production masks are produced from this updated database.

Via Programmability

In the context of the layout of circuits designed for change, via programmability applies to circuitry that is truly designed to be programmed, such as read-only memories (ROMs) or specialized decoders that are configured independently from the base design.

In this case, the configuration of a circuit is driven by a “coding” scheme that is produced in general from a software development group. Implementing the coding scheme is done by the placement of vias on top of a programmable circuit.

There are two aspects to implementing a layout design for via programmability:

1. An unconfigured layout design that can accommodate all possible placements of vias. “Legal” sites should be designed into the leaf cells and assembled design. Legal sites for via placement are defined as locations where the resulting design would be design-rule correct under all conditions.

2. A methodology for placing or programming the vias onto the base layout design.

This is usually a macro that uses a polygon editor as the layout engine, or a customized CAD package that can read and produce a layout database in a standard format.

Via programmability using software is a common technique used in ROM design today, and it has the following advantages:

• Software designers for “on the chip” can optimize their code until late in the project schedule.

• If planned and implemented properly, the design is correct by construction and should always be DRC and LVS error free.

• Once the via programming technology is developed, it can be reused for sub- sequent evolutions in the underlying base layout. Only the “legal sites” of a new architecture need to be specified.

• An effective base layout design and programming scheme can include techniques to minimize the connectivity of devices by excluding vias in the programmed design. Reductions in power consumption and increase in speed result.

Figure 9.3 illustrates an example of via programmability for a small decoder used within MOSAID.

Test and Probe Pads

Test and probe pads are aids that are implemented into a design to enable product engineers to check the internal operation of a physical chip.

Test pads refer to pads of metal that are compatible for bonding; probe pads are much smaller and are intended for very specialized measurement devices.

Test pads are also defined to be only available on a wafer and are not intended to be bonded for the final product. These pads are uncovered by the passivation for the prototyping or evaluation phase and are covered by a glass isolation layer before it is packaged. In terms of ESD, they are less protected than regular pads because after testing they will not be connected to the pins of the package.

An example where test pads are used extensively is within DRAM designs that have internally generated power supplies for internal circuitry. The test pads are normal-size pads connected to internal supply powers such as VPP, VBB, VCP, and VBLP. During the prototyping phase, the test pads are used to determine if the internal power supply circuitry is functional. They are also used in production test to evaluate reliability and process characteristics of the memory over the life of the product.

Probe pads, on the other hand, are used exclusively for the preproduction debugging and evaluation stage. Product engineers use probe pads to check the

functionality and timing of internal nodes of chips that have not been qualified for production.

Probe pads can be placed anywhere on the die, since they are used when the die is completely unprotected (Figure 9.4). The size of the probe pads is dependent on the equipment that is used.

Historically, probe pads were not explicitly implemented, because a single via was big enough for the probes that were available. As layer geometries have shrunk, a single via has become too small for physical probing. Generally, a probe pad that is in the range of 1 mm2 is sufficient.

Probe pads should be implemented in layout as directed by the circuit designer. However, it is likely that almost all routed nodes should be probeable. Certainly, critical signals such as clock signals and datapath signals are prime candidates for probe pads.

It is important to document the probe pads coordinates carefully so that they can be easily found!