LAYOUT DESIGN TECHNIQUES IN AN UNCERTAIN ENVIRONMENT:ENGINEERING CHANGE ORDERS.

ENGINEERING CHANGE ORDERS

Engineering Change Orders or ECOs are part of being a layout designer. As a design nears completion, verifying and integrating changes becomes a significant problem. Using a controlled methodology, such as an ECO flow, to implement change ensures that the bug is reviewed from a broad level of architecture and all the possible implications of the change in one block are reviewed against all the other blocks’ interface points of view.

Engineering Change Orders are a formal methodology used toward the end of design projects so that changes are carefully implemented without delaying the project further. Using all of the methodologies that were presented, most changes would have minimal impact on layout design.

In terms of a procedure for implementing an ECO, there are as many ways of defining it as there are design flows and project management styles.

Conceptually, or from a management standpoint, an ECO procedure might look like the following:

1. The design is frozen on a given date with the understanding that full chip simulation and verification is ongoing.

2. At this point the layout may be in the last stages of finishing major blocks and the routing of the top level is 90 percent complete.

3. Any change from this point on is considered an ECO. The ECO is reviewed from a technical point of view to ensure that it is valid, and a ranking of its importance is determined. The impact on the project schedule is also estimated.

4. The project leader or manager reviews the ECO and decides whether it is to be implemented. ECOs are often rejected if the error is minor or can be corrected in a future version of the chip. Another criterion for evaluating an ECO is its relevance to the market or customer or the impact of delaying the chip’s entry into the marketplace.

5. If the ECO is to be implemented and shortcuts are necessary for it to be done on time, then special precautions may be taken to ensure that the ECO is done correctly. Examples might be having a second person inspect the implementation, or a staged release of the design.

In the case of an ASIC flow where place-and-route tools are used to generate the layout of the chip, the layout tools have an ECO flow built into the tools.

The ECO procedure outlined below is conceptually straightforward, but not always so in reality:

1. The new netlist is reviewed and an approach to address the change is generated.

2. The place-and-route tools are deleting cells that no longer exist in the netlist and try to place the new ones. In some cases, if the design was very crowded and there is not too much free space, the new cells may be placed far away from the previously deleted ones, redoing the cell placement. The problem is that in many cases the initial placement was optimized for power, electromigration, RC, etc., and the ECO may change the picture.

3. The router is ripping up the local routing and is trying to reroute the new connectivity. Most of the popular routers today can do it in 99 percent of the cases. If the router gives up, human eye and manual edits can finish the last 1 percent of the job.

4. After the place-and-route is done, an extraction of the layout is required to check if the changes achieved the timing goals and there is not too much change to the related circuitry. If not, additional iterations of the ECO flow are needed.