System Level Design Languages:TLM Advantages

TLM Advantages

Features and advantages of TLM over RTL modeling have made designers to move their design starting point from RTL models to transaction level models. Although it can be used for faster modeling, the main purpose designers use TLM is its simulation speed. Since the communications between modules are modeled with efficient and high-level functions and the computational modules are also modeled in a higher level of abstraction, designers can gain over 1000X simulation efficiency from TLM simulation over RTL simulation. The simulation efficiency leads to other TLM features including more efficient partitioning, faster and more precise functional verification, faster hardware/software coverification, and faster hardware/software cosimulation.

Some of the above features produce other benefits for the designers. For example, by modeling a system with TLM, the designer has a more comprehensible view for the design partitioning. A mature partitioning in a design can even affect the power consumption of the manufactured SoC.

Designing in transaction level provides designers and their costumers an early design prototype. This early prototype helps designers clarify whether the complete design is feasible to be developed and implemented. In this prototype, several critical decisions, improvements, and changes can be made to prevent the failure of an entire project. Without ESL, these critical decisions could only be made after spending a lot of time and money for developing an RTL prototype of the design. In addition to ESL, the software team can start its software development and verification with this early prototype. In traditional RTL designs, the software team has to wait for completion of the RTL design before starting the software development.

Different Levels in TLM

The following lists include the expressions that are used by companies and organizations, for description styles that can be considered as transaction level.

The OSCI organization has proposed the following views for various levels in TLM:

• Programmers view (PV): This level of modeling is a pure functional modeling at the very early stages of the design. The timing is not specified in details or there is no timing at all.

• Programmers view with timing (PV + T): This level of modeling is used to refine the PV level without major changes in the system functions written in the PV level. In this level, a PV and an interface (e.g., a FIFO interface) exist in the design.

• Cycle callable (CC): In this level of modeling, the design must be developed to work cycle- by-cycle. This level of modeling is cycle-accurate. The interfaces are developed to have a specified task in each cycle. Also the functional models are altered to work correctly with cycles. This level is still considered as a transaction level and it is still simulated faster than RTL. This is because the interfaces still use higher-level ports and interconnections than the ports in RTL. This implies that a cycle callable or cycle-accurate model is different from a pin- accurate model.

The OCP-IP organization has its own defined levels of modeling that are listed below.

• Message Layer (L-3): This layer is very similar to the PV level described above. In this level, the design is described at the highest level of abstraction. It has no timing and it is event-driven. Each event contains several data. This layer is very practical for being used as a proof-of-concept model and for the first versions of partitioning.

• Transaction Layer (L-2): This layer contains more details than layer L-3. It is usually used for hardware/software partitioning, hardware performance analysis, and generation of a testbench for the design developed in the L-1 layer. The designs in this layer have an approximate timing and are structurally more accurate than the models in layer L-3, which means that the structure of the designs is closer to a real design than those in layer L-3.

• Transfer Layer (L-1): This layer is very similar to CC layer defined by OSCI. In this level, where we have a clocked cycle-accurate model, the interfaces are changed to be mapped onto the chosen hardware interfaces and bus structures. Similar to the CC layer, this layer is still higher than the RT level. L-1 models are useful for developing testbenches for RTL models. They can also be used for performance comparisons with RTL models. The RTL layer in this hierarchy is called layer L-0.

The above two sets of definitions are very similar. There are also other definitions for transaction levels based on these two sets definitions and are listed below.

CoWare defines the following set of design layers:

• Programmers view (PV)

• Architects view (AV)

• Verification view (VV)

There is also another set of design levels defined by ST-MicroElectronics [9]:

• SoC functional view (FV)

• SoC architecture view (AV)

• SoC micro-architecture view (MV)

Although the above groups and companies use different names and expressions for their definitions, they follow the same abstraction in each level. In a general definition, these abstractions include a functional level with poor or no timing, a lower-level architectural design with poor timing, and a cycle- accurate (but not necessarily pin-accurate) level with timing details. We can call these levels high-level transaction (HLT), medium level transaction (MLT), and low level transaction (LLT), respectively. All of these levels can be approximately mapped as shown in Table 86.1.