HDL-Based Tools and Environments:Test Tools

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Test Tools

Test tools used in design flow are divided into the following categories:

• Fault simulator: A fault simulator is a simulator that is capable to simulate a circuit in presence of faults. Because of the lack of fault model in the higher levels of abstractions, fault simulation is usually performed at the gate level. Fault simulation is normally done for the development of manufacturing tests, i.e., testing the manufacturing defects. A fault simulator receives the circuit gate-list and a set of test vectors and finds the fault coverage of a test vector. There are differentimplementations for fault simulators, such as serial fault simulation, parallel fault simulation, deductive fault simulation, and concurrent fault simulation.

• Automatic test-pattern generator (ATPG): ATPG is a program used to generate test patterns to test a circuit. An ATPG usually operates in conjunction with a fault generator program that creates the minimal collapsed fault list. There are many features that are important in test generation, including the cost of test generation, the quality of the generated tests, and also the cost of applying tests. Several implementations of ATPGs are exhaustive test generation, random test generation, and path-sensitized test generation.

• Test advisor: This program usually performs a testability analysis on the circuit being designed and based on this analysis, proposes testability techniques to increase the testability of the circuit. There are several types of the test advisor program including programs used to select scan register and programs used to insert a BIST architecture in the design. These tools are usually used in conjunction with synthesis tools.

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