System Verilog:Complete Design Example

Complete Design Example

In this section we describe a 4-bit add-and-shift multiplier using System Verilog. The multiplier accepts two 4-bit numbers and multiplies them to generate an 8-bit product. The multiplier has a 4-bit input inbus, for inputting the multiplier and multiplicand, and a 4-bit output outbus for outputting the 8-bit product as two 4-bit numbers. The multiplier looks for a complete pulse on the start input and then in the next two clock pulses reads the multiplier and multiplicand and stores them into the internal registers X and Y, respectively. The next four clock pulses are used to perform multiplication. When the 8-bit product is ready, the done output becomes 1 for two clock pulses. During this period the least and most

significant 4-bits of the product are put on the outbus output. Figure 90.37 illustrates the block diagram of the multiplier partitioned into data and controller parts.

The data path of the multiplier of Figure 90.37 is partitioned into functional units (adder), memory elements (registers and shift registers), and buses (tri-state buffers). Figure 90.38 shows the block diagram of this data path. The Y register holds the multiplicand and the X shift register holds the multiplier. The 8-bit multiplication result is stored in both A and X registers. In each step, the X0 bit is examined and if it is equal to 1 contents of Y will be added to A. Then both A and X are shifted one place to the right. Here, these two operations (addition and shifting) have been performed in a single clock pulse.

The multiplier controller, which is a finite-state machine, is shown in Figure 90.39. In the idle state, the controller searches for a complete pulse on start. In two consecutive states the required control signals are issued to load the multiplier and multiplicand in X and Y, respectively. In the next four states, based on the value of X0, the addition of A and Y is performed and both A and X are shifted right.

The adder used in the data-path is a 4-bit adder that adds the partial product with the multiplicand. Figure 90.40 shows the description of the adder.

Figure 90.41 shows the description of a 4-bit positive edge-triggered register with two synchronous inputs clr and ld. Two instances of this register will be used to store the multiplicand, i.e., Y, and to store the partial products, i.e., A, in the data path.

The next module is a 4-bit positive edge-triggered shift register with two synchronous inputs, ld and shft. With a positive edge of the clk, if ld = 1, the 4-bit input d is loaded into the shift register, otherwise if shft = 1, the content of the shift register is shifted right 1 bit and its left-hand bit is filled by ser_in. Figure 90.42 shows the description of the shift register. One instance of this module (labeled X) is used in the data path to hold the multiplier value.

As shown in Figure 90.43, the mux2to1 module is a 4-bit 2-to-1 multiplexer with two 4-bit inputs i0 and i1, a sel input and a 4-bit output y.

Figure 90.38 shows how the above components should be interconnected to each other to build the multiplier data path. We will use an interface, called bus, to interconnect the multiplier data path and controller. As illustrated in Figure 90.44, bus contains nine signals named clrA, ldA, ldX, ldY, shft, add, AOnObus, XOnObus, and X0. The modes of the interface signals are specified by two modport constructs called dp_mode and cu_mode. For instance all signals are considered as inputs of the data path except X0 which is an output.

Consider Figure 90.45 which shows the data-path description. As shown in this figure, an interface of type bus is declared as data-path port. Its mode, specified as dp_mode, declares all signals as input except X0, which is declared as output. Interface signals can be accessed using interface instance names followed by “.” together with the signal name. For instance expression dp_bus.clrA is used to access the clrA signals. As shown in Figure 90.39, the multiplier controller is designed as a finite-state machine. The Huffman coding style is used to describe the controller shown in Figure 90.46. An interface of type bus is declared as the data-path port, and its mode is specified as cu_mode.

The interconnection of the multiplier and the data path to build the multiplier is shown in Figure 90.47. An instance of the interface bus is used to interconnect these two components.

Figure 90.48 illustrates a typical test-bench developed to test the multiplier. This module uses an instance of the multiplier called circuit under test (cut), and applies 10 pairs of random data to the multiplier with an initial block.