Register-Transfer Level Hardware Description with SystemC:The Role of RTL SystemC in Hardware Design.

The Role of RTL SystemC in Hardware Design

Although digital design technology has powerful hardware description languages like VHDL and Verilog, the need for RTL SystemC is still justified. Generally, a system specification, implemented at the system level of abstraction, must be mapped to hardware (such as an IC, SoC, or board). Therefore, after system- level design (for example in SystemC), there must be an easy way to feed designs to a synthesis tool for obtaining a netlist of gates or low-level components. Since most of the available synthesis tools only support RTL designs, we have to convert our high-level system descriptions to their corresponding RTL models. There are two ways to perform this: (1) refining the system-level design in SystemC to RTL SystemC, and (2) redesigning the system-level design in SystemC with another HDL (like Verilog).

The first solution has certain advantages. Since refinements are performed in the same environment, the conversion process will be faster than recoding it in another language. Besides, it is more error-free to refine different parts of a design than to recode the whole design in another language. Another advantage of the first solution is that after developing the RTL model, the designer still has the opportunity to cosimulate the hardware and software parts together.

Therefore, to reach the synthesis process from the system-level design, RTL SystemC design plays an important role in the design flow. Today, there are high-level synthesis tools that convert a high-level design, developed in C language, to RTL SystemC. Furthermore, there are converter tools for converting RTL SystemC descriptions to VHDL and Verilog languages. These processes together enable designers to go from system-level down to a netlist of gates with transition through SystemC.

Another scenario in which knowledge of RTL SystemC becomes useful is in design reuse. To be able to use existing VHDL or Verilog components in design of systems at the system-level in C or C++, these designs must be translated to SystemC and then used along with higher level components described in C++. Whether this translation is done manually or automatically, knowing SystemC is useful for verification of the translated codes or manually performing the translation.