ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN:CHIP FINISHING CELLS

CHIP FINISHING CELLS

After all the devices related to the logical functionality of the chip are placed and verified, there is still work to be done in implementing a class of cells to finish the chip and ensure that the chip is compatible with the manufacturing process.

Examples of chip finishing cells include the following:

• Alignment keys for processing equipment

• Structures for process monitoring, dicing, and packaging

• Identification marks that may be big enough to see with the naked eye: logos, designer initials, maskright and copyright markings, process identification, layer identification (Figure 5.30)

In many cases, the manufacturer completes these tasks and the circuit designer does not have to worry about them. At minimum, the layout designer should receive all of this information ahead of time, to allocate space for the required devices; otherwise, there is a danger that there will not be enough free space on the chip to implement them.

It is important to note that after all the devices are placed and verified individually, the final full chip verification should include all of these chip finishing cells that will be included in mask making. It is easy to cause an electrical problem by placing an identification mark in the wrong place.

Alignment Keys

There are many alignment keys in layout design, depending on the process and manufacturing requirements. Figure 5.31 shows three examples of alignment keys.

The laser fuse alignment key is one that has to be instantiated at least three times. Depending on the manufacturer, the key is made of various layers that can be seen from the chip level. Metal and via layers are typical choices.

The NIKON keys are used to align the reticle when generating the masks on the wafer. Every layer is placed in this key; therefore, these cells will never pass layout verification because they will generate design rule errors and illegal devices. NIKON keys need to be placed in all four corners of the chip and as close to the corner as possible.

We have explained here only a few of the various keys related to fuses and packaging. There are also many keys used by process people during prototyping and robots during mass production to monitor the status of the manufacturing process.

There are process monitors to measure transistor performance, mask alignment, and layer resistivity and capacitance, as well as layer widths and spaces.

The placement of the process monitors is generally a function of the mask- making process in that these monitors must be a part of every mask set. If a mask set consists of only one chip, then the monitors need to be placed within the die area. In the case where multiple chips coexist within a single mask set, the monitors can be placed between die.

During manufacturing tests, bad die are identified with a black dot, and these die will be rejected when the wafer is diced.

Scribe and Seal Ring

Chips are never manufactured one piece at the time. They are manufactured on a large slice of silicon called a wafer. Once the wafer is manufactured, the wafer is diced into individual ICs.

Narrow channels between individual ICs are mechanically weakened by scratching them with a diamond tip. This channel is known as the “scribe” channel. The wafer is cut along the scribe with a diamond blade, or burnt with a laser. The wafer is then mechanically stressed and broken apart along the channels, thereby separating the individual ICs. Figure 5.32 documents this concept.

In order to protect the IC, a seal ring is required that is implemented around the edge of the chip.

For some chips that must have substrate connected to a source other than the normal VSS, there is another ring around the chip that is in many cases called the “seal ring.” For example, many DRAMs incorporate the memory cell in isolation from the normal logic. In such cases the NMOS devices are placed in a retrograde well that is connected to a voltage source called VBB that is biased to a negative voltage. To generate this voltage and others, the memory chips have built-in charge pumps. If the external logic is connected to VBB and the entire periphery must have substrate connected to VBB, a VBB seal ring is laid out

around the chip. This “seal ring” is placed outside the pad area but before the scribe. The reason is that, placed outside the pad area, the seal ring will not impede any other signals and/or circuits and can be connected directly to the VBB pump. Figure 5.33 shows a seal ring example. Note the VBB pump position: it should be as close as possible to the seal ring.