ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN:LASER FUSE CELLS

LASER FUSE CELLS

Considering the complexity of the different types of IC design: microprocessors, graphic accelerators, ASICs, etc., there are literally millions of simulations that have to be done before the chip is free of bugs (errors). The problem is that in many cases the market is pressing the design team to release the design before all the combinations of simulations are done. Another problem could be that by the time the chip is designed, the manufacturing process has evolved so that the transistor characteristics are somehow altered. Designers are constantly trying to take these issues into account. However, these precautions may not be enough to com- pensate for poor results in silicon.

DRAM memories are especially susceptible to process defects even though the process is highly optimized for the core layout. The memory cells, wordline drivers, sense amplifiers, and y-decoders are highly susceptible to failure for this reason. Memory designers have extensively used the concept of redundant circuitry to repair faulty circuitry, thus increasing the overall yield of the manufacturing process.

Repairing DRAMs once they have been fabricated in a production environment is typically done with laser programmable fuses. DRAM designs contain spare wordline drivers, sense amplifiers, and y-decoders that can be enabled once failures are detected and identified. A laser physically “blows” fuses that will disconnect the failing portions of the chip and replace them with the spare elements.

An alternative use of laser fuses is to provide circuit adjustment options for manufactured ICs. Similar to bond options or metal options, laser fuses can be used to configure the operation or performance of a chip.

Fuses are generally implemented in polysilicon or metal and must be built in such a way that a laser repair machine can accurately blow them out. As you can imagine, the fuses must be specially designed to isolate the impact on the rest of the internal circuitry of a laser zapping the chip. These areas need to be exposed at least temporarily, so there is a danger of contamination during this time.

As in the design of pad cells, there are physical requirements to be satisfied. For example, the fuses must be large enough for the laser repair machine to accu- rately program them. A list of guidelines for fuse layout would include the following:

• A design where the fuses are equally spaced is more compatible with the laser repair machine. These machines typically move to a starting point and move at a consistent speed; therefore, equal spacing of fuses is ideal.

• Similarly, minimizing the number of rows of fuses reduces the overhead of moving the laser to new starting points. Fuses will be designed in running rows placed as close as possible to each other, so movement of the laser head without blowing them should be reduced to a minimum. See Figure 5.28 for details.

• The number of fuses should be optimized so the repair time for each chip can be minimized.

• Scrambling equations have to be very clearly documented so the testing people can program the machine easily without errors.

• Special keys alignment keys for the laser repair machine are required. These ensure that the laser is exactly aligned from the start and can be done auto- matically. These keys usually must enclose the area where all fuses are located.

Please refer to the CD-ROM for color layouts taken from a MOSAID design. There is one example from a DRAM process and one from an ASIC process. Figure 5.29 shows another example.