LAYOUT DESIGN FLOWS:SYSTEM ON A CHIP, OR SOC

SYSTEM ON A CHIP, OR SOC

The hottest design flow today (1999) is system on a chip, or SOC. This is the case when there is a need for a very big and complicated chip and there is no time to design everything from scratch.

The magic words in these types of chips are design reuse and intellectual property (IP) blocks. In design reuse, the individual blocks are design from the start with reuse in mind. The disadvantage to this methodology is that time to have a block designed for reuse is longer than a normal flow. The reasons are obvious:

• The specifications must cover common problems, not just specific ones for the current project

• More general-purpose simulations must be done

• If the blocks are implemented in a specific process, then the architecture will not be custom designed for it

• Additional consideration must be given to process variations

There are, however, big advantages when reusing the block as a core for future designs:

• Preservation of the IP—some experts may be busy on the next design (or have left the company)

• Time to design the second or third one is lower by up to 50 to 70 percent, depending on the kind of the imported block (hard, soft, etc.)

• The block or concept was verified in silicon, a fact that gives the next design team confidence that the block works

In terms of the entire design flow a SOC design will be a mix and match of different flows based on the type of each particular block. There might be control blocks done in an ASIC style and analog blocks or memories that require full- custom techniques. The integration of all of these block types is the real challenge of SOC design.

Let’s see now how we can determine a flow that meets the requirements of SOC designs. The flow will depend on many factors and should be determined after many issues are understood. Here are some things to consider:

• Technology selection: What kind of process will be used? In the case of embedded memory, perhaps a blend process will do it.

• Type of board on which the chip will be assembled: From this it may be possible to determine the packaging type, footprint, die size, price, pin positions and assignment, and power consumption limitations.

• Availability of core/blocks internally or on the external market sold by vendors: Are they soft or hard cores?

• Libraries available for the chosen process: Are they silicon proven? What power consumption, speed, and tools are they compatible with?

• Levels of testability to be addressed in the design: This is another hot topic of the year—design for testability (DFT).

• Limitations of the manufacturing process: Time frame, special layers, reticle limitations, packaging limitations, etc.

• Reliability of the chosen process: Is it experimental, first-time trial, proven over a few working chips?

In terms of layout, the biggest job in these designs is to prepare a hierarchical design that has clear definitions of all the interfaces between blocks, whether internal or imported—floorplanning. Importing IP blocks can be tricky if the provider did not take into consideration any available standards such as those set by the Virtual Socket Initiative Alliance (VSIA), or if the process is not the same.

Blocks may be “soft” in that they are not process specific and need to be care- fully implemented in the target process. In the case of “hard” blocks, the layout must be instantiated or migrated at the block level, extracted, and back annotated into the simulation to check timing and functionality in the new process.

No matter how up-to-date the flows presented here may be, by the time this book is on the market, design engineers, process specialists, and software developers will have found new problems. Remember that we, the user community, have interesting jobs in which we must use creative thinking to solve day-to-day design problems.