System Verilog:Hardware Design with System Verilog

Hardware Design with System Verilog

System Verilog provides several design abstraction levels including switch level, gate level, RT level, and behavioral level. Here, we will focus on behavioral level hardware description.

Behavioral Modeling Constructs

Verilog as has several fundamental behavioral constructs, such as if-else, case, for-loop, and while-loop. This section describes how System Verilog enhances these constructs.

The Unique and Priority Modifier

System Verilog adds two modifiers, unique and priority that are used with if-else and case statements. These modifiers specify the way in which simulation and synthesis tools interpret the if-else (case) conditions. The unique modifier is used to make sure that only one condition in a series of if-else-if is true. This means that all conditions can be interpreted in parallel. However, the priority modifier is used to force the simulation or synthesis tools to interpret the condition as they appear in the code.

As an example, consider a barrel shifter with a 4-bit data input d, a decoded 4-bit shift amount input s, and a 4-bit data output y. Table 90.2 shows the truth table for this barrel shifter while its description is shown in Figure 90.24.

Figure 90.25 shows our barrel shifter using the unique modifier. In this case, if two or more conditions become true simultaneously (e.g., s[2] == 1'b1 and s[0] == 1'b1), a run-time error will be generated.

Figure 90.26 shows our barrel_shifter using the priority modifier. Here, if two or more conditions become true simultaneously (e.g., s[2] == 1'b1 and s[0] == 1'b1), the first condition that appeares in the code (i.e., s[2] == 1'b1) will be met, and the corresponding statement (i.e., y = {d[1:0], 2'b00}) will be executed. These modifiers can be applied to case statements in the same manner.

For Loop Enhancement

System Verilog enhances the for loop statement by allowing

• Local variable declaration in the initial part of a for loop

• Multiple statements in the initial and update part of a for loop

Figure 90.27 shows an example of a for loop that employs these enhancements.

Do-While Loop

System Verilog adds a C-like do-while loop. The loop’s termination condition is tested at the end of the loop, which means that the loop body is executed at least once.

Combinational Circuit Design

Combinational circuits can be described using an always block. To do so, all inputs of the circuit should appear in the sensitivity list of the always block. In addition all combinational outputs should get a value for all possible combinations of the inputs. As an example, consider Figure 90.28 that shows a 2-to-1 multiplexer implemented with the if-else construct. As shown, all inputs (i.e., i0, i1, and s) are listed in the sensitivity list, and the y output requires some value for all input combinations.

Verilog-2001 allows the use of wild-card * in the sensitivity list of an always block as always @ (*) or always @*. This implies that each variable used as an input of the always block, i.e., variables read by always block, should be implicitly considered in the sensitivity list. If there are several signals that the always block is sensitive to, the use of the wild-card * shortens the code and prevents the user from probable coding errors. Figure 90.29 illustrates a 2-to-1 multiplexer with an enable input. In this example always @* infers always @ (i0 or i1 or s). Note that the wild-card * does not infer the variables used in the function called by the always block. For example, in Figure 90.29, function enable that uses variables g1 and g2_b, is called in an always block. As a result of using wild-card *, g1 and g2_b are not listed in the sensitivity list and therefore they cannot sensitize the always block for execution.

System Verilog adds a new procedural block, named always_comb, to resolve the discussed problem. The always_comb procedural block is similar to always @(*), with the difference that it infers all variables that the procedural block is sensitive to, including variables used in functions called in the procedural block. Figure 90.30 illustrates the multiplexer example using always_comb. In this case the procedural block is sensitive to variables i0, i1, s, g1, and g2_b. The procedural always_comb block cannot contain any explicit event or timing control. In addition any other assignment to the variables assigned in the always_comb block is not permitted. The always_comb block should describe a combinational logic. In other words, outputs should never retain their value from one activation to the next.

Level-Sensitive Latch

An input combination in an always block, where the output is not assigned a value represents a level- sensitive latch. Consider the gated latch with two inputs g and d, and an output q described in Figure 90.31. Any change in d or q triggers the always block and if g = 1, q gets the value of d, otherwise q holds its previous value. This performance describes the latching behavior.

System Verilog provides a new procedural block, called always_latch, to describe latching behavior. As an always_comb block, the always_latch block infers all variables that the procedural block is sensitive to, including the variables used in functions called in the always_latch block. The always_latch should describe a latch, which implies a condition where the output does not get any value for at least one input

combination. As with always_comb, any other assignments to the latched output are not allowed outside the always_latch block. Figure 90.32 shows the gated d-latch using always_latch.

Edge-Triggered FF

If an always block is sensitive to the positive or negative edge of a signal, it can usually be synthesized as an edge-triggered sequential circuit. Verilog-95 provides two operators posedge and negedge, which can be used to show sensitivity to the edge of a signal. As an example, consider Figure 90.33 that shows an example of a positive edge-triggered d-ff with active low asynchronous aclr input.

System Verilog also provides an always_ff procedural block to show the behavior of an edge-triggered sequential circuit. All signals in the sensitivity list should be used by a posedge or negedge operator. Any

other assignment to the sequential output is not allowed outside the always_ff block. Figure 90.34 shows the d-ff of Figure 90.33 using an always_ff block.

Interfaces

There are two types of port connections in Verilog-95: connection by position and connection by name. Using these methods in a hierarchical design makes the creating and maintenance of connection procedure difficult. For example, Figure 90.35 shows an example of an add-and-shift multiplier, which is partitioned into data_path and controller parts. These two parts are connected using several wires. As shown in the figure these wires should be declared as ports in both modules, as well as being declared in the top-level module. Finally, they are used in both module instances to make interconnections.

System Verilog provides a new port type called interface. Interface is a group of signals that can be used as a single port. As shown in Figure 90.36, an interface is declared using the interface keyword, followed by an interface name. Then a list of interconnection signals should be declared. Usually the interface signals are declared as inputs in some modules and declared as outputs in some other modules. Therefore, the port mode should be specified by using the modport construct, which is similar to the port declaration of a module excluding the port type. For example, in Figure 90.36 there are two types of modports, dp_mode and cu_mode. The endinterface keyword shows the end of the interface declaration. Now the interface can be used in module port declarations by using the interface name followed by a modport name (see Figure 90.36). Then the interface should be used in a top-level module to interconnect the modules. To do so an instance of the interface is needed to be used in the port connection. Note that the modport cannot be used in both module declaration and module instantiation.