Integrated circuit course

INTERCONNECT ROUTING After we have solved power routing and clock tree issues, we can attack the general routing requirements. Special signal requirements will be discussed in Chapter 7. Let’s review the proper order for routing signals: 1. Power supplies 2. Clock signals 3. Buses 4. Special signals—to be discussed in Chapter 7 5. General routing—the topic of this section Routing Plan The goal of a routing plan is to determine the overall complexity of the routing to be implemented, identify areas on the die specifically for routing only (these areas are known as routing channels), and address potential bottlenecks or prob- lems in achieving a completely routed design. In addition, the impact of the routing on the final chip area can be estimated. For example, dedicated routing channels can be estimated and included in a chip floorplan. Here is a list of steps to achieve a viable routing plan. 1. Signal Estimate. Without a final schematic or netlist, it is

Computation Temporal Logic In this section, theory and practice of model checking and related topics are first introduced and then CTL and its application in specification of properties will be described. Formal Verification The need for reliable hardware systems is an important issue and the involvement of these systems in our daily life is increasing day by day. The rapid growth of technology inquires into the methods that increase our confidence in the correctness of these systems. To increase the level of this confidence, we highly need robust techniques to verify these systems. Simulation is the traditional approach for verifying finite-state systems, but its problems are: working much slower than the real system, being expensive and having no guarantee for all possible input combinations to be simulated. For these reasons, the application of formal verification (FV) is increasing every day. Formal verification is the process of checking whether a design satisfies for requirements (

CHIP FINISHING CELLS After all the devices related to the logical functionality of the chip are placed and verified, there is still work to be done in implementing a class of cells to finish the chip and ensure that the chip is compatible with the manufacturing process. Examples of chip finishing cells include the following: • Alignment keys for processing equipment • Structures for process monitoring, dicing, and packaging • Identification marks that may be big enough to see with the naked eye: logos, designer initials, maskright and copyright markings, process identification, layer identification (Figure 5.30) In many cases, the manufacturer completes these tasks and the circuit designer does not have to worry about them. At minimum, the layout designer should receive all of this information ahead of time, to allocate space for the required devices; otherwise, there is a danger that there will not be enough free space on the chip to implement them. It is important t

MEMORY DESIGN LEAF CELLS Memory layout design is a real challenge to a newcomer. The design of memory- related layout cells requires detailed knowledge of both the manufacturing technology and the circuit architecture and performance issues. In most design styles, there are portions of memory such as SRAM, but the most challenging is the dynamic random access memory, or DRAM. Figure 5.21 shows a floorplan of one implementation of a DRAM core. First we have to see how a basic memory cell looks in a circuit (Figure 5.22). This is because the manufacturing process is most complex, as shown in Figure 5.23. The stacked capacitor DRAM memory cell has special layers that form the memory cell capacitor. Any DRAM memory cell layout is generally very process specific, and company confidential as well. As Figure 5.23 shows, the DRAM memory cell is very high (tall) in terms of the manufacturing process. Generally the node and plate poly layers are allowed for use only in the memory cell are

POWER GRID Power supply lines such as VDD and VSS are the most pervasive signals on the chip. Consider that they connect to virtually every gate and block; they each have many pins on the package; and they carry a lot of current and therefore must be sized appropriately. The need to manage power issues very carefully in IC design has grown over time. More complex chips result in larger power grids. Voltage levels on chips have been decreasing over time from 5 V to 3.3 V, but the operating frequencies have increased. The net effect is that the power consumption of ICs today has increased. There are also many more low-power applications with cell phones, PDAs, and laptop computers. These applications really benefit from power management techniques. CAD automation for power management has been developing as well and this adds another area of expertise to study and master. The logistics of implementing a power grid requires planning and should be one of the first things to consider whe

LASER FUSE CELLS Considering the complexity of the different types of IC design: microprocessors, graphic accelerators, ASICs, etc., there are literally millions of simulations that have to be done before the chip is free of bugs (errors). The problem is that in many cases the market is pressing the design team to release the design before all the combinations of simulations are done. Another problem could be that by the time the chip is designed, the manufacturing process has evolved so that the transistor characteristics are somehow altered. Designers are constantly trying to take these issues into account. However, these precautions may not be enough to com- pensate for poor results in silicon. DRAM memories are especially susceptible to process defects even though the process is highly optimized for the core layout. The memory cells, wordline drivers, sense amplifiers, and y-decoders are highly susceptible to failure for this reason. Memory designers have extensively used the

PLANNING TOOLS There needs to be a planning phase for all layout design tasks, but in general a floorplan starts from the chip level down to the block level. The idea behind this methodology is to build everything bottom-up while using the top-level floorplan to define the block interfaces and to coordinate updates to these interfaces as portions of the design are completed or verified. Chip Floorplanning Tools Floorplanning is the process of identifying structures that should be placed together and allocating space for them so as to meet the conflicting goals of avail- able space (cost of the chip), required performance, and the desire to have every block connect seamlessly to everything else. In most chips, the smallest design is also the highest performance design. Therefore, area and speed are characteristics that go hand-in-hand. A block or chip that is small in area has shorter interconnect lines, less routing, faster end-to-end signal paths, and even faster and more consisten