COMPUTER-AIDED DESIGN (CAD) TOOLS FOR LAYOUT:LAYOUT GENERATION TOOLS

LAYOUT GENERATION TOOLS

Layout generation tools are the main bulk of the layout design tools on the market today. Different tools are used depending on the level of abstraction, and this ranges from cell- or transistor-based layout to chip assembly. Each of these will be covered in this section.

Cell-Level Layout Generation Tools

Cell-level layout generation tools manipulate polygons to form transistors and connections between them.

Polygon Pusher. The most popular tool for cell-level layout generation is still the “polygon pusher” or basic “layout editor.” Theoretically, a polygon pusher can be used to design a complete chip of any kind from transistor level and up. However, it is not practical for block or chip assembly.

Polygon pushers are used to generate low-level cells, ranging from 10 to 100 transistors, and for drawing all the layers required in a VLSI process. These tools are very mature, and generally minimum maintenance is required. However, some companies have invested a lot of time to “enhance” the basic tool with macros to generate layout that is done repeatedly.

Polygon pushers provide an environment for very high-quality full-custom layout, but they are completely manually operated and thus are slow. Enhancements to the environment are constantly being developed in an attempt to add automation to speed up certain stages of the design process: N-well generation, contact cells, transistor generators, ports macros, etc.

Almost all the big IC CAD vendors offer a layout editor, so it is important to evaluate them in terms of the availability of add-ons for automation. With only a few exceptions, most of them are running on UNIX machines, but they are beginning to migrate toward PCs as well.

Applications for layout editors include the following:

• Full-custom VLSI layout, where size is the most important factor. Pitch limited layout in DRAM, SRAM, PLA, pad output buffers, and input protection devices are only a few examples where the pure polygon pusher is still needed as it is.

• Analog design and special process cells or keys.

Features of layout editors include the following:

• They enable the user to do layout design of any kind.

• They are easy to set up for any process and most of the time work out of the box.

• Minimal training is required to get started. Advanced layout designers designing analog circuits, for example, need to understand layout concepts more than features of the tool.

• Over time, most companies have customized and have built entire method- ologies around their layout editors. This is the main reason why stand-alone automated tools have not been able to displace them so far.

• Layout generation is very process dependent, so it made sense in the past to do everything in a 100 percent full-custom manner. ASIC flows and place- and-route changed the way people thought in terms of layout design.

• There are many internal tools inside big companies for this specific task that require a CAD group to develop and maintain the design environment. In many cases political interests are against progress and efficiency. Startup companies do not have to deal with such problems, so they are easily accepting new tools.

• These tools are slow compared to automated tools, and that is why they are rarely used alone. More and more they are mixed with complex device generators, transistor place-and-route, symbolic editors, compactors, and routers. All the vendors who have a large customer base are working hard to improve them by adding some type of automation.

Device Generators. Device generators with routers can be used to implement almost all levels of layout complexity. Most of them are very specific to low-level or transistor-level layout design in different applications.

The tool is used to generate low-level cells, and/or complete standard cell libraries, very fast and efficiently. In this case each cell is limited to ~10 to 100 transistors per cell and all the layers required in a VLSI process are drawn.

Setting up and maintaining this type of tool requires extensive knowledge. Device generators provide the best mix of layout automation and full-custom design possible for cell generation.

Advanced device generators available today are schematic or netlist driven so the result is correct by construction. Knowledgeable drivers (layout designers) can work wonders using this “enhanced layout editor.”

Applications for device generators include the following:

• Standard cell libraries, where standardization of the pin assignment, cell height, neighboring requirements, etc., is an important factor in layout design

• Cells for datapath, where the tool and design requirements have to be guar- anteed and tailored to specific designs

• Applications where quality and analog requirements are as important as layout design speed Features of device generators include the following:

• Layout generation is fast, but the tools are expensive for a small company.

As we write, the prices of these type of tools are dropping because of com-

petition. This is supposed to be the next generation of the basic layout editor.

• The tools have to be set up by an experienced user, but then can be used by any new trainee. For special layout requirements, experts in layout design and macros may be required, but these cases are typically only 10 percent of the effort in cell design.

• They are fast compared to full-custom polygon pushers, which is why they have gained market share in the past 5 years; however, they are slower than silicon compilers.

• These tools provide a good environment for process migration and/or process changes during the design process—processes evolve during the 1 to 2 years of a project’s design time.

In principle, the market for silicon compilers is moving toward regular structures and block-level layout, while device generators are aiming to replace the old polygon pusher.

Cell Placers. Cell placers are used for optimizing the placement of individual devices and layers. In many cases a device generator is combined with a cell placer and a cell router to provide a complete layout environment. Ideally, cell placers need to understand cell architecture for good results.

Following are some features of cell placers:

• The numbers of devices and pins that these tools handle are small (hundreds), but the placement optimization is very detailed. Many constraints are considered.

• Ports can be placed on all sides. The placement may be fixed or may “float,” in that it can be changed if a better layout can be achieved.

• Regions for PMOS and NMOS transistor placement are controlled—for example, transistors can be placed in rows of variable heights and may include multiple rows of different heights.

• Transistor fingering is automatic, based on specified architectural constraints.

• Substrate and well connections can be controlled.

• Layout that is already complete can be imported. This is useful in the case where a rough layout is done by hand and given to an automated tool to finish the job.

• The interface to the cell router is seamless.

At this level, placers really enhance the layout designer’s speed and productivity. There are very few noticeable disadvantages of using placers in cell- level layout. Using a placer is a big step forward in increasing the amount of cell-level layout automation. The only barrier to their use is that they have to be easy to set up and use, and because they are used by designers who are very comfortable with polygon editors, these tools need a very good graphical user inter- face. Historically, all text-based tools have failed here.

Cell Routers. Routers for cell-level layout are typically very simple. However, some vendors have carved a niche by promoting the features of cell-level layout to the requirements of chip-level assembly. There are a few good cell routers on the market, and it is important to have a device generator, a placer, and a router in the same environment. If driven by a netlist, cell routers can accelerate cell generation. The most powerful routers allow the user to define constraints such as the following:

• Equal length of signals—a full bus of signals will have exactly the same lengths for all bits

• Special line widths for predefined signals or applying special requirements interactively

• Power routing constraints

• The number of contacts for each connection and/or the minimum contacts for a source/drain

• Differential pair routing

Compactors. A compactor can be used at almost all levels of layout complexity. Most of them are best used at a transistor or cell level. The tool is used to compact transistor layout and their connections inside a cell design.

One approach to using this type of tool is for the layout designer to do a loose job and run the compactor to optimize the layout. This is a very fast and efficient methodology to generate DRC clean layout cells.

For cell-level layout, the setup and maintenance of a compactor requires a very knowledgeable designer. The advanced compactors that are available today, together with schematic or netlist-driven layout generators, can provide the best of all worlds because the result is correct by construction and should pass both DRC and LVS checks. In the case where the compactor works on symbolic layout data, the results are extremely fast, and they can add advanced structures such as jogs within a wire if required.

Compactors are used at any level of design—from transistor-level layout to top-level routing, compactors should be part of any layout environment!

Features of compactors include the following:

• They are capable of generating very quickly most kinds of layout, as well as correcting DRC errors before the errors are made.

• Any novice can use the tool if experts have properly validated the setup of the tool.

• Compactors are sometimes used for a limited process migration and/or process changes during the design process. When processes evolve during the 1 to 2 years of a project’s design time, a compactor can fix minor design rule changes.

• For the moment, compactors are running in flat mode or within only one level of hierarchy. There may come a day when a “push-button” tool will be able to compact a full chip to fix a design rule change.

Silicon Compilers. Silicon compilers can also be used to design cells of various levels of layout complexity. Similar to compactors, most compilers work best at the transistor or cell level of layout design. The tool is used to generate low-level cells, and/or standard cells that are limited to ~10 to 40 transistors per cell, very quickly and efficiently while drawing all the layers required in a VLSI process.

Silicon compilers require extensive and expert maintenance to be effective in a changing environment. They provide the fastest cell generation possible. A standard cell library can be generated in ~1 day while customizing the cells for a specific placer and/or routing tool.

Applications for silicon compilers include the following:

• Standard cell libraries, where standardization of the pin assignment, cell height, abutment, etc., is an important factor in layout design

• Cells for datapath, where the tool and design requirements have to be guar- anteed and tailored to specific designs

• Any time speed is the most important factor in a layout generation Following are some features of silicon compilers:

• Layout generation is fast, but the tools are expensive for a small company.

For example, silicon compilers for standard cell libraries are so expensive that only companies selling libraries as their main product can justify their purchase.

• Only highly trained people in software, i.e., software engineers and/or designers with broad background in software, can use the tools. They may know how to run the tool, but not necessarily how the layout is supposed to look and be used. We hope this book will help them to understand more about generating layout for the entire design process.

• There are many internal tools inside big companies for this specific task that require a CAD group to set up, develop, and maintain the design environ- ment. Standard formats are used to interface the output of silicon compilers with the other tools in the flow. The problem with using standard formats is that specific information that is required for the compiler may be lost and the advantage of using the tools defeated.

• They are so fast compared to full-custom polygon pushers that they have gained a lot of market-share in the past 5 years. Silicon compilers can be used not only for layout generation, but for process porting as well.

• Some compilers are targeted to specific applications: RAMs, ROMs, PLAs, I/O cells, standard cells, datapath designs, etc. These compilers do not require as much training because they have been designed for novice users.

Consider silicon compilers to be a suite of tools that contain device genera- tors, placers, and routers under the hood. They do not offer the capability of inter- active editing that is available by using the combination of the three individual tools.

Block-Level Layout Generation Tools

In general, block-level layout does not deal with transistors but with small cells and macros that are built with one of the tools described in Section 10.3.1. At the block level of layout design there are three types of tools. For regular structures, tilers are described, and for nonregular placement and connectivity, placers and routing tools are described.

Tilers. A tiler is used to automate the generation of very organized and repetitive structures such as memories, datapath circuitry, and pad frames. The GUI is generally quite primitive, and they are available as a stand-alone tool or integrated in various design tools environments.

A tiler is a simple placer that understands a predefined or preprogrammed architecture and places leaf cells in the arrangement that is defined. A tiler simply executes a set of layout instructions (tiling program) and does not optimize or reconfigure a design based on a netlist or constraints. The layout generation part of a memory compiler is the most common form of a tiler.

Advanced tilers support decision constructs (i.e., if–then–else) and para- meters in its tiling language. This feature enables a tiler to be configurable based on a set of parameters, and this is the basis for flexible memory compilers. For example, if the choice of cell is dependent on a specific parameter, then this can be built into the tiling program. The strength of a buffer can be chosen and tiled appropriately this way.

Following are some applications for tilers:

• RAMS, ROMS, PLA, I/Os, DATAPATH, etc.

• New migration tools are using tilers to break apart a particular design hierarchy and provide this information to the migration tool so that the leaf cell abutment constraints can be automatically generated.

Features of tilers include the following:

• The power of a tiler can be used as a very fast area estimation tool. A representative set of cells can be tiled quickly to obtain an estimate of area for a chip or a block. If routing is added and extracted, an estimate of interconnect delays is possible and is especially valuable in an ASIC design flow.

• Any novice can use the tool if experts have properly validated the setup of the tool.

• Tilers are generally not expensive.

Block Placer. At the block level, placement issues are quite a bit different from those at the cell level. The block placer is one of the main tools used in an ASIC design flow. They are commonly known as the placement part of a place-and- route tool and are critical to the future of layout design as chips grow in size and complexity.

The size of the netlist is the first difference and in this case may be hundreds of thousands of cells and signals with many thousands of ports entering the block. This size of design is impossible to do manually in a reasonable amount of time. In practical terms, manual methods are limited to blocks with ~500 cells.

The block placer is a sophisticated tool to be able to handle large designs. This tool uses complex algorithms to optimize and reoptimize the placement of cells to achieve a placement that will meet timing, area, and routability constraints. This is not a simple task, as the tool needs to manage these trade-offs effectively.

One way to understand the role of a placer is to understand the inputs to the tool:

• A netlist of the circuit design that contains a list of cells to be placed and the logical connectivity between the objects to be placed.

• A description of each cell in the design. The description includes characteristics such as size, pins, pin locations, power consumption, and timing characteristics.

• Total available area and placement of ports to the block. In the case of cell- based placement the placer needs row information such as size, direction, channel restrictions if any, and location of black boxes or hard macros.

• In the case of a gate array, the location of the legal sites where cells are allowed to be placed.

• If advanced features such as power grid evaluation, IR drop per row, or electromigration rules are to be used, the constraints of each cell and for the entire design.

The output of a block placer is a preliminary version of a design where all cells have been placed in a specific location and the design is ready for routing to be completed.

Placement based on timing constraints is available and is a new and much more stringent methodology to use. In this case the placer has to evaluate placement based on the timing constraints received from the design file.

Block placers typically have a useful graphic user interface and are gener- ally easy to set up. Block-level placers are essential to increase the productivity in layout design.

As discussed in detail in the next section, routing approaches have been either channel- or area-based. Channels are routing areas between cells, while area-based routers use all available area to route a design.

The placer that is used in a particular design must work closely with the router and must understand the limitations of the router. For example, a placer optimized for channels should not feed a completed design to a maze router.

Channel-based placers work on the basis that an infinite amount of area is available for routing and that routing channels can be expanded or compacted to accommodate and optimize the size of the channels. Cells are placed in rows, and the row that is chosen for a specific cell is determined based on the best place for routability and other constraints such as timing or power. The placement algorithm can vary the number of rows and the length of the rows to achieve a design that will meet all of the routing constraints.

Maze-based placers simply place all cells in rows within a fixed area without regard to dedicated routing channels; they assume the routing is completely over the cells. The placement algorithm considers issues such as routability, congestion, and timing, among many other things.

Block Routers. As the name implies, a router automatically completes the connectivity of a placed design. Connections are implemented between cells and the interface to the block or chip. Routers in general can be used at all levels of layout design for all methodologies.

Features of block routers include the following:

• Routers automate the task of connecting millions of signals while optimizing for things such as area, timing, and power. This capability cannot be replaced by manual techniques.

• Effectively using both routers and placers requires a significant amount of experience to take full advantage of the many features built into the routers available today. Routers are not effective right “out of the box” and most companies have dedicated experts for this task.

• Some designers are reluctant to give up control of the routing to an automatic tool. However, confidence in extraction methodologies is usually sufficient to alleviate concerns and the speed of routing is hard to beat. Routing techniques are useful for nontraditional applications such as analog, RF, and memories, and it may be market forces that promote the use of routers in these areas.

A brief history of routers is presented next. It is useful to understand the evolution of the tools because it can give us a lot of insight into the concepts behind routing tools today.

Historically, routers were initially developed as a tool to assist or automate existing block layout methodologies for processes that were available at the time. Only one or two layers of metal were available; thus, routers had to work within the same constraints as the layout designer.

Routing channels were used extensively. The first routers had algorithms specifically targeting channel routing and are now known as channel routers. These routers essentially optimized the routing in one direction, that being the height of the channel.

As more routing layers became available, different algorithms were developed to take advantage of the extra layers. With three or four available layers, channels became unnecessary because routing could be implemented directly over the cells and the cells could be placed adjacent to each other without wasted space in between. In this case, maze routers became dominant because the “maze” algorithms built into the routers optimized the routing based on a mesh or two- dimensional maze of routing resources.

Finally, more recently, shape-based routers have appeared to address the chip-assembly or transistor-level designs. Shape-based routers are much more powerful in terms of implementing customized routing, but they are very limited in capacity when compared to maze and channel routers. Channel and maze routers are able to handle large databases because they essentially work on a point-to-point basis and use a well-defined and coarse grid. Shape-based routers implement polygons, and therefore need to manipulate much more information. A description of shaped-based routers follows in Section 10.3.3.

In terms of block routing, channel and maze routers are most relevant to our discussion.

In Chapter 5 we described how the architecture of the standard cells defined how the routing was done, and we gave a specific example of layout using channel routing. How does a channel router work in this environment?

At the beginning, with only one or two routing layers, the first routers connected signals only between the boundaries of the cells. Routing was optimized within the channels to reduce the number of signals within any particular channel. When three routing layers became available, channel routers were enhanced to be able to route over the cells and take advantage of the fact that the ports of the cells were in the middle of the row.

Channel routers optimize the size of different channels as an initial analysis step and require a specific algorithm to do a good job. This analysis ensures that the routing can always be completed, but the problem with this assumption is that the block may end up being too large for the space allocated to it.

Channel routers then automate the layout of channels by understanding the routing architecture and its limitations. The tools offer additional features such as the following:

• Automatic addition of jogs in wires to reduce the total size of the block.

• Automatic reduction of the number of vias by optimizing any jumpers to preferred routing layers. This is a very useful feature when the routing is between two blocks with only busses between them and no other passing signals. This feature also helps reduce chip size and signal resistance.

• Adding via topologies based on a specified formula and not limited to a simple fill algorithm.

• For symbolic channel routers, easy manual switching of a signal from one channel to another and to run compaction to fix DRC errors.

• Timing-driven placement and power analysis (offered by most today).

• For some routers, built-in routines that interactively adjust power connections, tapering, routing widths and positions, etc. For small geometries, delay and power calculation is necessary.

• For other routers, timing analysis built into the tool that can be done before or after routing so the designer can adjust certain routing parameters before completing the final route. In general, the timing is based on pin-to-pin delays.

• Current calculations built into some tools that provide many sets of data such as absolute current in a wire, the current density in the wire, and supply voltage for every node and cell.

• In most routers, ECO capabilities. However, remember that a complicated change many increase the size of the block/chip!

Channel routers have some disadvantages as well. The biggest disadvantage of channel routers is the uncertainty of block or chip size, which is not fixed until all the routing is done. The second is that they impose restrictions on the design of the standard cell library. For instance, cell pins may be required to be aligned in a single row or to be positioned on the border of the cell.

As mentioned previously, channel routers became less effective when chips began to be manufactured using four layers of metals. At this time maze routers achieved maturity, and extraction in an ASIC flow became standard procedure. Using a maze router, a design can be cell limited and routing channels are not required. This feature made chip size estimation easier and the size of a block or design could be determined earlier in the overall process.

Maze routers do not work with channels, but attempt to complete the routing using an area-based approach where connectivity is optimized based on horizon- tal and vertical routing resources. The available area must be predetermined and constrained for the router so that signal lines stay within a fixed area.

Different algorithms are used within maze routers. Generally, a global routing algorithm is used to subdivide the total area, a detailed router to complete signal routing, and a clock tree routing algorithm and a power routing algorithm for power supplies. All of the algorithms are linked together to complete a final design.

Unlike a channel router, where a route will complete every time, there is no guarantee that the maze router will be able to route all nets. Routing congestion and/or impossible timing constraints are the likely culprits that prevent the completion of a routing job. The best way to address these issues is to modify the placement of the cells. In some cases, for the last 10 or 100 nets, human intervention may be able to finish the job.

Routability problems are best solved by changing the placement of the cells, and this is why a strong link between the router and placer is needed. In this case the placer can place objects that are router friendly, and this is only possible if the placer understands the algorithms of the router. This is why it is highly recommended that the placer and router come from the same company.

ECO functionality is available within maze routers to implement minor changes in the design. Existing nets can be locally removed and then reconnected based on the new design.

In terms of worldwide use, most ASIC houses are using maze routers not only for standard cells and gate arrays, but also for FPGA designs.

After the blocks are routed and simulated with extracted parasitics, it is usually time to insert any clock trees. The placement is generally the starting point for clock tree insertion, as the distribution of loads is known. In this case the routing tool has another algorithm to find the cells that are connected to a specific clock and is placing and routing only the buffers and clock signals to minimize clock skew. (See Figure 10.6.)

A measure of quality for place-and-route is what is known as utilization. The utilization of a design is defined by the ratio of the area consumed by cells to the total available area. Channel-based designs will have a lower utilization number because of the overhead of channels. Gate array designs limit cell density by having limited cell placement sites and in this case utilization factors will be in the range of 50 to 70 percent. Maze routers will have the highest utilization factor because of the flexible cell placement and over-the-cell routing. Nevertheless, the cells are placed in rows, and not every row will be 100 percent full, so the utilization will not be 100 percent.

Remember that placers that work with maze routers use a fixed die size and do not include a compaction step. Therefore, there is no way to improve efficiency of a design after all the routing is done.

Combining the approach used in channel routers of routing analysis, placement then compaction with the efficient routing algorithms of maze routers pro- vides the best of both approaches.

The concept is that a channel-based placement is done that fully evaluates the design for optimal routability, and after placement the “channels” or rows are compacted to determine the final block size. It is this final block size that the maze router uses to complete the routing. Since a channel-based placer has the freedom to define the number and length of rows, the routability of the final design will be much higher than the output of a maze-based placer. This is because a maze- based placer is given the available area and cannot change the aspect ratio of the block to improve routability.

With this optimized design size, the maze router will more easily complete the routing and the overall effect should be an improved utilization factor. The big players (vendors) in the place-and-route tools market are trying to implement a similar approach in different ways.

Chip Assembly Tools

Chip assembly, as the name implies, is the process of combining the different blocks of a chip with the pad cells and integrating them all into a completed design. Consider the following scenario:

• The layout leader designed a chip floorplan using a tool for placement of blocks.

• The blocks had their pins identified compatible for routing.

• A router was used to connect the blocks.

• The plan was updated during the course of a project by doing the following:

As each block was finished, its empty box was replaced with the final block layout The routing was updated to reflect the new position of pins and widths of the signals An analysis of this process should conclude that the chip assembly was completed near the beginning of the project in the form of the “initial” floorplan! With the help of automated tools that are available today, this flow is not a dream, but completely possible.

In general, for top-level assembly or routing between blocks that number no more than 50 and pins and signals that number no more than 5,000, shape-based routers are the best tools for the job.

Shape-based routers are very rich in features, but have the disadvantage of limited capacity. Channel and maze routers simply connect pins and respect obstruction layers using simple paths on a coarse grid. Shape-based routers have many features that include connecting a signal of different widths using polygons. Therefore, shape-based routers need to process a lot more information, and this is what limits their capacity.

Shape-based routers produce layout that is full-custom. Historically, these routers were based on approaches taken from printed circuit board layout tools where very controlled and detailed layout is required.

Most routers are automatic, but more and more users are asking for inter- active features for routing. Some shape-based routers are already providing features that have never been available before:

• One bit of one signal of a bus can be routed manually, and then the shape of this bit can be copied relatively easily to all the bits of the bus.

• Busses can be routed together as a group with options to run them at 45- degree angles or around corners to minimize bus skew or routing area.

• Routing of signals can be constrained by grouping them in classes such as busses, special groups, or clocks.

• User-defined routing rules for each layer as well as net-based routing constraints address analog signal crosstalk, minimum capacitance, and resis-tance effects.

These routers were the first to offer automatic shielding to reference signals and diode application against antenna rules, thus demonstrating their PCB heritage.