LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS:MULTIPLE RULE SETS

MULTIPLE RULE SETS

People working with ASIC processes generally have an easier time doing layout, as they have the benefits of having a relatively simple set of design rules. The total number of rules is less than the set of rules used by designers in DRAM or embedded memory processes.

Why do memory processes have significantly different rules from anything else? Because the memory cell fills 50 to 70 percent of the entire chip area, the memory cell itself is an extremely customized design with its own set of rules and specialized layers as well. As a reliability measure, memories have redundant circuits included on the die so failures in the array can be replaced.

Defining a final set of design rules is a very complex process in which circuit designers, layout experts, and process people have to trade off many factors: price, size, complexity, tolerances, design easiness, reliability of the process over the area of the chip and wafer, etc.

In terms of design rules, a DRAM memory has three different rule sets: one for the memory cells and their friendly cells, one for the pitch-related logic inter- facing to the memory cells, and one for the periphery layout outside of the

memory array. The rules for the periphery layout may be similar to those for an ASIC process within the same process generation.

Table 8.1 shows an example of the definition of three rule sets for a DRAM process.

The layout of designs with multiple rule_sets must be done in such a way that the different set of rules can be verified using the DRC verification tool. The fundamental problem is identifying in the layout database areas that are to be checked with specific sets of design rules.

Three example methodologies are given below:

1. Each region defined by one particular set of rules is implemented using a separate set of layers. Masks are created from a database of merged layers once the layout verification is complete. This methodology requires the layout designers to switch layers in different regions, but once this is done, the regions are easily manipulated.

2. Each region is defined by a special layer called a blocking layer. General layout is done using the same layer in all regions, and once they are complete, the desired blocking layer is drawn. Within the layout verification tool, intermediate layers are generated to separate the polygons for each set of design rules as demonstrated in Table 8.2.

3. Regions are identified by a cell naming convention. The layout verification tools are set up to recognize and identify different regions by the name of a cell. In this case, the general layout is done with one set of layers, and once this is complete, the cell is named appropriately. This approach is simple; however, it relies on the fact that the layout can always be divided into discrete cells that do not overlap.