LAYOUT DESIGN:INTRODUCTION TO TRANSISTOR LAYOUT

INTRODUCTION TO TRANSISTOR LAYOUT

Before we start to discuss the layout of transistors, let us review the schematic fundamentals presented in Chapter 2. The top half of Figure 3.6 shows the basic symbol representations of both PMOS and NMOS transistors. The length and width of the transistors are shown. Also remember that the bulk connection is there, but is hidden from view to avoid cluttering the schematic.

In Chapter 2 we stated that the amount of current flow is determined by the device size. We hinted that the current flow is increased as the width of the device is increased or the length of the device is decreased. Let’s see why this is by under- standing the physical characteristics of the transistor as determined by the layout of the device.

Figure 3.7 shows a simple MOS transistor layout. Note the following:

• All four terminals of the transistor are shown and labeled.

• The gate of the transistor is defined by a polygon of polysilicon.

• Areas of active or diffusion adjacent to the gate of the transistor define the source and drain areas. Note that the source and drain labels are in fact interchangeable!

• This transistor happens to be a PMOS transistor and the active areas are doped P-type by the P+ implant layer.

• This PMOS transistor is located in an N-type well called an N-well. This forms the transistor bulk node.

• An N-type active area (without the P+ implant layer) forms a connection to the N-well because the N-well and active areas are of the same type (N-type).

• The source, drain, and well connection are themselves connected by another contact layer. This contact layer would typically be the contact layer for the first layer of metal.

• The width and length are labeled correctly. The width is greater than the length!

The length and width of a transistor are the two most important dimensions of a transistor that we need to fully understand.

As we stated previously, when people in the industry talk about the gate size of a specific technology, they are referring to the minimum gate length. Note the following:

• In terms of layout design, the length of the transistor is the distance between the source and the drain of a transistor. This may not be intuitive, because the physical dimension of the transistor length is smaller than the width. The next paragraph should explain the reasoning behind this convention.

• In terms of transistor performance, the length of the transistor is the distance electrons have to travel when the gate is “on” or “open” to produce a mea- surable current flow. Remember, it is the gate voltage that controls the flow of current. If the distance between the source and drain is reduced, the gate voltage has a stronger influence in enabling current flow. The bottom line is that in the same process technology, if two transistors have the same width but different lengths, the transistor with the shorter gate length will produce more current. More current conceptually means faster performance.

• The length of a transistor in terms of manufacturing capabilities is the narrowest possible piece of polysilicon (poly) that can be manufactured reliably. Smaller poly dimensions and thus smaller transistors results in smaller ICs, so it is attractive to use the minimum gate length to minimize chip area.

Let’s now consider the width of a transistor.

The width of a transistor should be thought of as the number of parallel channels that are available for current to pass from the source to the drain. Wider transistors have more channels available; more channels mean more current.

Once again comparing two transistors, this time each having identical gate lengths but different gate widths, the transistor with the larger gate width will produce more current.

To help you remember the convention of transistor length and width, think of a transistor like a bridge. The length of the bridge is the distance between the two sides of the river and the width of the bridge is the number of lanes of traffic that the bridge can accommodate. The amount of traffic that can cross the bridge is limited by the length and width of the bridge in the same way that current is limited by the length and width of the transistor.

If the design of the bridge is to allow 100 cars to cross over in 1 minute, then the bridge needs to be made wide enough to achieve this goal. In most cases the length of the bridge is fixed (similar to the minimum allowable gate length) and the only degree of freedom we have to achieve our goal is to adjust the width.

One last concept to consider. There are cases when we might want a slow or weak transistor! This is easily achieved by minimizing the width of the transistor and/or increasing the transistor gate length. Delay elements or weak feedback devices are examples where slow transistors are desired. It may turn out that in these cases the gate length does turn out to be greater than the width (Figure 3.8).

The first important thing to remember is the difference between the length and width of a transistor and how to apply this to transistor layout! For completeness, Figure 3.9 shows the layout of an NMOS transistor.

• This NMOS transistor is not located in any type of well and thus sits in the bare substrate. In this case, the substrate can be deduced to be P-type. The substrate forms the transistor bulk node.

• A P-type active area (with the P+ implant layer) forms a connection to the substrate because the substrate and active areas are of the same type (P-type).

Bulk Connections

Now that we know how the two basic kinds of transistors work and look, let’s review the bulk connection node and see how it is connected. This is most easily understood by understanding a cross-section of the wafer and transistor. Note

that a layout designer can only understand this concept and cannot influence its design.

Most (but not all!) raw silicon wafers these days are P-type, so of the two transistor types, an NMOS transistor is the easier to design. The transistor layout is simply implemented in the bare substrate (see right-hand side of Figure 3.10).

To generate PMOS transistors we need to create a separate bulk node and therefore need another layer. This is typically called an N-well; when implemented, it forms an island of N-type substrate. Implementing P-type active regions within this N-well creates a PMOS transistor with a bulk connection as defined by the N-well (see center area of Figure 3.10).

The left-hand side of Figure 3.10 also shows an NMOS transistor design that has a different bulk node than that of the substrate. A retrograde well (R-well) or P-type well (P-well) has been implemented in the N-well. This region creates a separate P-type bulk node for the transistors implemented within this region. This is an example of substrate connection in a DRAM process.

In the case of an N-type wafer, the polarities of the transistor connections are simply the reverse of those shown previously. Figure 3.11 shows substrate connections for an inverter in an ASIC process.

Conductors and Contacts

From a layout design point of view, conductors and contacts are straightforward. Let’s look at the formation of contacts from a manufacturing point of view so that as layout designers we can understand their use and limitations.

Different technologies have drastically different process definitions. A typical ASIC process has one type of polysilicon for the gate and two to four types of layers of metal for interconnection. An advanced ASIC process can have up to six layers of metal for interconnect and use a low-level metal called metal0 for source/drain connections. For DRAM memories, a typical process today has four types of polysilicon and three to five metals for interconnectivity. In any of these cases the conductor layer definition for the process is quite complex.

There is a subtle difference in the industry between the names contact and via. A contact typically refers to the lowest level metal hole that contacts from the lowest level of metal to the polysilicon or diffusion layers. The holes that allow higher layers of metal to connect between each other (e.g., metal1 to metal2 or metal2 to metal3) are called “vias” or “through holes.”

We will use vias throughout this text and for easier understanding of these holes. For an illustration of contacts and vias, please refer to Figure 3.12.

As you can see from the cross-section shown in Figure 3.12, there are various isolators between the various conductor layers. I1 is the isolator between the diffusion regions and polysilicon. I2 is the isolator between the diffusion regions and metal1. A hole in this isolator generates a “contact” between the passing metal1 and the lower active source/drain layer. I3 is the isolator between metal1 and metal2, and a hole in it represents a via.

In most cases there is a distance to respect between the “contact” hole and the “via” hole, but in most modern processes the via can be placed on top of the contact. In some very complicated processes where the size of the chip is very important (read cost), the process may allow all the vias to be aligned one on top of each other. They are called “stacked” via processes.

Each metal has various characteristics in terms of resistance (R), capacitance (C), and topology requirements. Something to think about is that the higher metal layers in the process require more vias to connect down to the transistor layers. These vias add resistance. We will analyze later in the book how to deal with these electrical characteristics of the process and how to take advantage of them.

Inverter Layout

Now that we have all the basic concepts of transistor layout design, let’s once again look at the simplest combination of transistors, the inverter (Figure 3.13).

As you can see, the transistor representation is very simple, and now we are able to generate a layout since we know how a transistor looks and where it is connected. Let’s see what we can observe from analyzing Figure 3.14.

• The PMOS is connected to VDD in the schematic as well as in layout.

• The NMOS is connected to VSS in both pictures.

• NMOS and PMOS transistors have the same IN signal on their gates and same OUT on their drains—in both pictures.

• The widths are different—the PMOS is twice as big as the NMOS transistor in this example.

• The lengths look similar, but they are different, and the difference cannot be seen.

• For N-well there is a N+ connection to VDD. This connection is implied in the schematic.

• For substrate there is a P+ connection to VSS. This connection is implied in the schematic.

The design of this inverter will be presented in later sections, and this inverter is shown to give us an idea of how a complete layout cell should look.