Architecture and Design Flow Optimizations for Power-Aware FPGAs:Low-Power Circuit Techniques.

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Low-Power Circuit Techniques

Now let us look at some circuit techniques for reducing power in FPGAs. An obvious approach would be to resize all transistors for optimal power. Since this approach applies equally well to any integrated circuit, we do not discuss this further. Instead, in this section, we describe some of the techniques proposed specifically for FPGAs.

One technique to reduce dynamic power consumption in the routing is to use a low-swing interconnect circuit, which uses a lower voltage in the routing fabric. A drawback of most conventional low-swing techniques is the slow speed of the receiver circuit, and the short-circuit current at the receiver end. George et al. [7] mitigated this problem by employing cascode circuitry and differential circuits at the receiver (see Figure 20.6). They assumed pass-transistor switches in the switch blocks, and modified the drivers and receivers for connections with the CLB output and input pins, respectively. This low-swing circuit reduced the energy by a factor of 2 over full-swing interconnect when VDDH of 1.5 V and VDDL of V were used.

Another circuit technique uses redundant memory cells to reduce leakage energy (see Figure 20.7). Routing multiplexers in FPGAs are usually implemented in multiple stages to reduce parasitic capacitance in intermediate or output nodes and to minimize the number of programmable memory cells. For example, a two-stage implementation of a pass-transistor-based multiplexer is shown in Figure 20.7(a). It is composed of several smaller multiplexers, and to reduce the total number of SRAM cells, the same

Architecture and Design Flow Optimizations for Power-Aware FPGAs-0094

SRAM cell configures one pass transistor from each multiplexer in stage 1. When this mux is used, one of the paths from the inputs to the output is activated. However, since all small muxes in stage 1 share their select signals, each of them pass one of their inputs to their outputs. This drives the intermediate nodes 1, 2, 3, and 4 to VDD or VSS (depending on the value of the input passed by the corresponding state 1 mux), which in turn keeps the drain-to-source voltage, VDS, of all disabled pass transistors as VDD or VSS. Under these conditions, the disabled pass transistors with VDS = VDD contribute to leakage power. Figure 20.7(b) shows a low-leakage technique where the pass transistors that are not included in an enabled interconnection path are turned off and the subthreshold leakage current through a series of connected NMOS devices determines intermediate node voltage [9]. Although such an implementation requires additional SRAM cells for granular controllability, they reduce the leakage current of pass transistors in disabled input-to- output paths. Since these SRAM cells can be easily optimized for leakage by high-Vt devices, the impact on total leakage power due to integration of additional SRAM cells is minimal.

Leakage can also be reduced by inserting sleep transistors to cut off the supply to unused portions in an FPGA. Since the FPGA contains a large number of unused transistors for any given user design, sleep transistors can be very effective. Assistance from the CAD tool can further enhance the effectiveness of the sleep mechanism, as discussed in Section 20.7. However, a fine-grained insertion of sleep transistors can perform well enough without much CAD support (e.g. Ref. [26]). We refer the reader to Lodi et al. [10] for some low-leakage designs for the FPGA routing switch.

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