Dynamic Random Access Memory:Basic DRAM Architecture.

Introduction

The first dynamic RAM (DRAM) was proposed in 1970 with a capacity of 1 Kb. Since then, DRAMs have been the major driving force behind VLSI technology development. The density and performance of DRAMs have increased at a very fast pace. In fact, the densities of DRAMs have quadrupled about every three years.

The first experimental Gb DRAM was proposed in 1995 [1,2] and remains commercially available in 2000. However, multi-level storage DRAM techniques are used to improve the chip density and to reduce the defect-sensitive area on a DRAM chip [3,4]. The developments in VLSI technology have produced DRAMs that realize a cheaper cost per bit compared with other types of memories.

Basic DRAM Architecture

The basic block diagram of a standard DRAM architecture is shown in Figure 55.1. Unlike SRAM, the addresses on the standard DRAM memory are multiplexed into two groups to reduce the address input pin counts and to improve the cost-effectiveness of packaging. Although the number of address input pin counts can be reduced by half using the multiplexed address scheme on the standard DRAM memory, the timing control of the standard DRAM memory becomes more complex and the operation speed is

The CMOS DRAMs have several rapid access modes in addition to the basic modes. Figure 55.3 shows an example of the rapid access modes. The timing waveform shown in Figure 55.3 for DRAM operation is the page mode operation. In this mode, the row addresses are applied to the address pins and then clocked by the row address strobe RAS signal, and the column addresses are latched into the DRAM chip on the falling edge of CAS signal as in a basic READ mode. Along a selected row, the individual column bit can be rapidly accessed, and readout is randomly controlled by the column address and the column address strobe CAS. By using the page mode, the access time per bit is reduced.