Dynamic Random Access Memory:Gb SDRAM Bank Architecture

Gb SDRAM Bank Architecture

To consider the Gb SDRAM realization, the chip layout and bank/data bus architecture is important for data access. Figure 55.14 shows the conventional bank/data bus architecture of 1-Gb SDRAM [16]. It contains 64 DQ pins, 32 ´ 32-Mb SDRAM blocks, and four banks; and they all prefetch 4 bits. During the read cycle,

the eight 32-Mb DRAM blocks of one bank are accessed simultaneously. The 256-bit data is accessed to the 64 DQ pins and 4 bits are prefetched. In an activated 32-Mb array block, 32-bit data is accessed and associated with eight specific DQ pins. Therefore, it requires a data I/O bus switching circuit between the 32-Mb SDRAM bank and the eight DQ pins. It makes the data I/O bus more complex, and the access time is slower.

In order to simplify the bus structure, the distributed bank (D-bank) architecture is proposed as shown in Figure 55.15. The 1-Gb SDRAM is implemented by 32 ´ 32-Mb distributed banks. A 32-Mb distributed bank contains two 16-Mb memory arrays as shown in Figure 55.16. The divided word-line technique is used to activate the segment along the column direction. Using this scheme, each of the eight 2-Mb segments is selectively activated; sense amplifiers of one of the eight segments are activated; and all the 16-K sense amplifiers are activated simultaneously. As compared with the conventional architecture, the distributed bank architecture has a much simplified data I/O bus structure.